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An-Yeu Wu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. An-Yeu Wu, K. J. Ray Liu, Arun Raghupathy, Shang-Chieh Liu
    Parallel programmable video co-processor design. [Citation Graph (0, 0)][DBLP]
    ICIP, 1995, pp:61-64 [Conf]
  2. Kai-Yuan Jheng, Shyh-Jye Jou, An-Yeu Wu
    A design flow for multiplierless linear-phase FIR filters: from system specification to Verilog code. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:293-296 [Conf]
  3. Hung Yang Ko, Yi-Chiuan Wang, An-Yeu Wu
    Digital signal processing engine design for polar transmitter in wireless communication systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6026-6029 [Conf]
  4. Jen-Chih Kuo, Ching-Hua Wen, An-Yeu Wu
    Implementation of a programmable 64/spl sim/2048-point FFT/IFFT processor for OFDM-based communication systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:121-124 [Conf]
  5. Hsiu-Ping Lin, Nancy Fang-Yih Chen, Jyh-Ting Lai, An-Yeu Wu
    1000BASE-T Gigabit Ethernet baseband DSP IC design. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:401-404 [Conf]
  6. K. J. Ray Liu, An-Yeu Wu
    A Multi-layer 2-D Adaptive Filtering Architecture Based on McClellan Transformation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1999-2002 [Conf]
  7. An-Yeu Wu, K. J. Ray Liu
    A Low-Power and Low-Complexity DCT/IDCT VLSI Architecture Based On Backward Chebyshev Recursion. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:155-158 [Conf]
  8. Tsung-Han Tsai, Cheng-Hung Lin, An-Yeu Wu
    A memory-reduced log-MAP kernel for turbo decoder. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1032-1035 [Conf]
  9. I-Chyn Wey, Lung-Hao Chang, You-Gang Chen, Shih-Hung Chang, An-Yeu Wu
    A 2Gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1074-1077 [Conf]
  10. Chia-Tsun Wu, Wei Wang, I-Chyn Wey, An-Yeu Wu
    A scalable DCO design for portable ADPLL designs. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5449-5452 [Conf]
  11. Chi-Li Yu, An-Yeu Wu
    An improved time-recursive lattice structure for low-latency IFFT architecture in DMT transmitter. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:250-253 [Conf]
  12. Ching-Hua Wen, Huai-Yi Hsu, Hung Yang Ko, An-Yeu Wu
    Least squares approximation-based ROM-free direct digital frequency synthesizer. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:701-704 [Conf]
  13. Kai Huang, Fan-Min Li, Pei-Ling Shen, An-Yeu Wu
    VLSI design of dual-mode Viterbi/turbo decoder for 3GPP. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:773-776 [Conf]
  14. Meng-Da Yang, An-Yeu Wu
    A new pipelined adaptive DFE architecture with improved convergence rate. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:213-216 [Conf]
  15. Cheng-Shing Wu, An-Yeu Wu
    A novel cost-effective multi-path adaptive interpolated FIR (IFIR)-based echo canceller. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:453-456 [Conf]
  16. Meng-Da Yang, An-Yeu Wu, Jyh-Ting Lai
    High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:2, pp:218-226 [Journal]
  17. Huifei Rao, Jie Chen, Changhong Yu, Woon Tiong Ang, I-Chyn Wey, An-Yeu Wu, Hong Zhao
    Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1803-1806 [Conf]
  18. Jhao-Ji Ye, You-Gang Chen, I-Chyn Wey, An-Yeu Wu
    Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:869-872 [Conf]
  19. Chih-Hao Chao, Yen-Lin Kuo, An-Yeu Wu, Weber Chien
    A Power-Aware Reconfigurable Rendering Engine Design with 453MPixels/s, 16.4MTriangles/s Performance. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1113-1116 [Conf]
  20. Wei Wang, I-Chyn Wey, Chia-Tsun Wu, An-Yeu Wu
    A portable all-digital pulsewidth control loop for SOC applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  21. Kai-Yuan Jheng, Yi-Chiuan Wang, An-Yeu Wu, Hen-Wai Tsao
    DSP engine design for LINC wireless transmitter systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  22. Chia-Tsun Wu, Wei Wang, I-Chyn Wey, An-Yeu Wu
    A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  23. Wein-Tsung Shen, Chih-Hao Chao, Yu-Kuang Lien, An-Yeu Wu
    A New Binomial Mapping and Optimization Algorithm for Reduced-Complexity Mesh-Based On-Chip Network. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:317-322 [Conf]
  24. An-Yeu Wu, K. J. Ray Liu
    Algorithm-based low-power transform coding architectures: the multirate approach. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:707-718 [Journal]
  25. Jyh-Ting Lai, An-Yeu Wu, Chien-Hsiung Lee
    Joint AGC-Equalization Algorithm and VLSI Architecture for Wirelined Transceiver Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:2, pp:236-240 [Journal]

  26. A 52-mW 8.29mm2 19-mode LDPC decoder chip for mobile WiMAX applications. [Citation Graph (, )][DBLP]


  27. An efficient methodology to evaluate nanoscale circuit fault-tolerance performance based on belief propagation. [Citation Graph (, )][DBLP]


  28. Cost-effective echo and NEXT canceller designs for 10GBASE-T ethernet system. [Citation Graph (, )][DBLP]


  29. Low-power traceback MAP decoding for double-binary convolutional turbo decoder. [Citation Graph (, )][DBLP]


  30. Traffic- and Thermal-Aware Run-Time Thermal Management Scheme for 3D NoC Systems. [Citation Graph (, )][DBLP]


  31. Multilevel Linc System Design for Power Efficiency Enhancement. [Citation Graph (, )][DBLP]


  32. Dynamic Channel Flow Control of Networks-on-Chip Systems for High Buffer Efficiency. [Citation Graph (, )][DBLP]


  33. Reconfigurable Color Doppler DSP Engine for High-Frequency Ultrasonic Imaging Systems. [Citation Graph (, )][DBLP]


  34. Robust Packet Detector based Automatic Gain Control Algorithm for OFDM-based Ultra-WideBand systems. [Citation Graph (, )][DBLP]


  35. On the Fixed-Point Properties of Mixed-Scaling-Rotation Cordic Algorithm. [Citation Graph (, )][DBLP]


  36. Location-Constrained Particle Filter human positioning and tracking system. [Citation Graph (, )][DBLP]


  37. Traffic-balanced IP mapping algorithm for 2D-mesh On-Chip-Networks. [Citation Graph (, )][DBLP]


  38. High-throughput dual-mode single/double binary map processor design for wireless wan. [Citation Graph (, )][DBLP]


  39. A Low Cost Packet Detector in OFDM-Based Ultra-Wideband Systems. [Citation Graph (, )][DBLP]


  40. Rapid IP Design of Variable-length Cached-FFT Processor for OFDM-based Communication Systems. [Citation Graph (, )][DBLP]


  41. A Shortened Impulse Response Filter (SIRF) Scheme for Cost-Effective Echo Canceller Design of 10GBase-T Ethernet System. [Citation Graph (, )][DBLP]


  42. A Robust Band-Tracking Packet Detector (BT-PD) in OFDM-Based Ultra-Wideband Systems. [Citation Graph (, )][DBLP]


  43. A New Early Termination Scheme of Iterative Turbo Decoding Using Decoding Threshold. [Citation Graph (, )][DBLP]


  44. On-Line MSR-CORDIC VLSI Architecture with Applications to Cost-Efficient Rotation-Based Adaptive Filtering Systems. [Citation Graph (, )][DBLP]


  45. A Channel-Adaptive Early Termination strategy for LDPC decoders. [Citation Graph (, )][DBLP]


  46. High-performance scheduling algorithm for partially parallel LDPC decoder. [Citation Graph (, )][DBLP]


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