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Ari Paasio: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Olli Lahdenoja, Mika Laiho, Ari Paasio
    Reducing the feature vector length in local binary pattern based face recognition. [Citation Graph (0, 0)][DBLP]
    ICIP (2), 2005, pp:914-917 [Conf]
  2. Olli Lahdenoja, Esa Alhoniemi, Mika Laiho, Ari Paasio
    A Shape-Preserving Non-parametric Symmetry Transform. [Citation Graph (0, 0)][DBLP]
    ICPR (2), 2006, pp:373-377 [Conf]
  3. Victor M. Brea, Mika Laiho, David López Vilariño, Ari Paasio, Diego Cabello
    A one-quadrant discrete-time cellular neural network CMOS chip for pixel-level snakes. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5798-5801 [Conf]
  4. Asko Kananen, Mika Laiho, Kari Halonen, Ari Paasio
    N /spl times/ 16 cellular test chips for low-pass filtering large images. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:461-464 [Conf]
  5. Lauri Koskinen, Ari Paasio, Kari Halonen
    3-neighborhood motion estimation in CNN silicon architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:708-711 [Conf]
  6. Mika Laiho, Ari Paasio
    Dynamically coupled multi-layer mixed-mode CNN. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5810-5813 [Conf]
  7. Mika Laiho, Ari Paasio, Kari Halonen
    Improved cell core for a mixed-mode polynomial CNN. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2004, pp:93-96 [Conf]
  8. Ari Paasio, Jacek Flak, Mika Laiho, Kari Halonen
    High density VLSI implementation of a bipolar CNN with reduced programmability. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2004, pp:21-24 [Conf]
  9. Ari Paasio, Kari Halonen, Veikko Porra
    CMOS Implementation of Associative Memory Using Cellular Neural Network Having Adjustable Template Coefficients. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:487-490 [Conf]
  10. Ari Paasio, Mika Laiho, Asko Kananen, Kari Halonen, Jonne Poikonen
    A 32×32 cellular test chip targeting new functionalities. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2003, pp:506-509 [Conf]
  11. Mikko Pänkäälä, Jonne Poikonen, Laura Vesalainen, Ari Paasio
    Realization of an analog current-mode 2D DCT. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:745-748 [Conf]
  12. Jonne Poikonen, Ari Paasio
    An area-efficient full-wave current rectifier for analog array processing. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:757-760 [Conf]
  13. Jonne Poikonen, Ari Paasio
    Rank identification for an analog ranked order filter. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2819-2822 [Conf]
  14. Laura Vesalainen, Jonne Poikonen, Mikko Pänkäälä, Ari Paasio
    A gray-code current-mode ADC for mixed-mode cellular computer. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2004, pp:81-84 [Conf]
  15. Kati Virtanen, N. Pankaala, Ari Paasio
    Compensation of errors generated by an analog 2D DCT. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6272-6275 [Conf]
  16. Mika Laiho, Ari Paasio, Asko Kananen, Kari Halonen
    Discrete time analog polynomial type CNN with digital state. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:497-500 [Conf]
  17. Ari Paasio, Asko Kananen, Kari Halonen
    Very fast and compact fixed template CNN realizations for B/W processing. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 1999, pp:595-598 [Conf]
  18. Mika Laiho, Ari Paasio, Asko Kananen, Kari Halonen
    Cell and network level design of a mixed-mode CNN. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:621-624 [Conf]
  19. Victor M. Brea, David López Vilariño, Ari Paasio, Diego Cabello
    Implementation oriented theory design issues on the DTCNN template generation. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2002, pp:101-104 [Conf]
  20. Lauri Koskinen, Ari Paasio, Mika Laiho, Kari Halonen
    Effect of CNN shape segmentation on MPEG-4 shape bit-rate. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:552-555 [Conf]
  21. Mika Laiho, Ari Paasio, Asko Kananen, Kari Halonen
    Realization of Couplings in a Polynomial Type Mixed-Mode Cellular Neural Network. [Citation Graph (0, 0)][DBLP]
    Int. J. Neural Syst., 2003, v:13, n:6, pp:443-452 [Journal]
  22. Lauri Koskinen, Ari Paasio, Kari Halonen
    Motion estimation computational complexity reduction with CNN shape segmentation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2005, v:15, n:6, pp:771-777 [Journal]
  23. Kati Virtanen, Janne Maunu, Jonne Poikonen, Ari Paasio
    A 12-bit Current-Steering DAC with Calibration by Combination Selection. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1469-1472 [Conf]
  24. Tero Koivisto, Teemu Peltonen, Meigen Shen, Esa Tjukanoff, Ari Paasio
    Sine wave as a correlating signal for UWB radio. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  25. Janne Maunu, Mikko Pänkäälä, J. Marku, Jonne Poikonen, Mika Laiho, Ari Paasio
    Current source calibration by combination selection of minimum sized devices. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  26. Kati Virtanen, Mikko Pänkäälä, Mika Laiho, Ari Paasio
    Implementation of an asynchronous current-mode ADC with adaptive quantization. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  27. Mika Laiho, Ari Paasio, Victor M. Brea
    Effect of mismatch on the reliability of binary-programmable CNNs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  28. Jonne Poikonen, Ari Paasio
    On the topographic equivalence between voltage mode and current mode ranked order filters for array processors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  29. Olli Lahdenoja, Janne Maunu, Mika Laiho, Ari Paasio
    A massively parallel algorithm for local binary pattern based face recognition. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  30. Mikko Pänkäälä, Kati Virtanen, Ari Paasio
    An Analog 2-D DCT Processor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2006, v:16, n:10, pp:1209-1216 [Journal]

  31. Architecture for Analog Variable Block-Size Motion Estimation. [Citation Graph (, )][DBLP]


  32. A one-quadrant discrete-time cellular neural network architecture for pixel-level snakes: B/W processing. [Citation Graph (, )][DBLP]


  33. Effect of mismatch on a ranked-order extractor array [image processing applications]. [Citation Graph (, )][DBLP]


  34. A Gray-coded digital-to-analog converter for a mixed-mode processor array. [Citation Graph (, )][DBLP]


  35. Template design for binary-programmable cellular nonlinear networks. [Citation Graph (, )][DBLP]


  36. A current-mode ADC with adaptive quantization. [Citation Graph (, )][DBLP]


  37. Parallel processor algorithm for variable block-size computation at low bitrates [video coding applications]. [Citation Graph (, )][DBLP]


  38. Centroiding and classification of objects using a processor array with a scalable region of interest. [Citation Graph (, )][DBLP]


  39. On the Spatial Distribution of Local Non-parametric Facial Shape Descriptors. [Citation Graph (, )][DBLP]


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