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Biplab K. Sikdar:
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Publications of Author
- Niloy Ganguly, Pradipta Maji, Sandip Dhar, Biplab K. Sikdar, Parimal Pal Chaudhuri
Evolving Cellular Automata as Pattern Classifier. [Citation Graph (0, 0)][DBLP] ACRI, 2002, pp:56-68 [Conf]
- Sukanta Das, Biplab K. Sikdar, Parimal Pal Chaudhuri
Characterization of Reachable/Nonreachable Cellular Automata States. [Citation Graph (0, 0)][DBLP] ACRI, 2004, pp:813-822 [Conf]
- Sukanta Das, Biplab K. Sikdar
Classification of CA Rules Targeting Synthesis of Reversible Cellular Automata. [Citation Graph (0, 0)][DBLP] ACRI, 2006, pp:68-77 [Conf]
- Pradipta Maji, Biplab K. Sikdar, Parimal Pal Chaudhuri
Cellular Automata Evolution for Distributed Data Mining. [Citation Graph (0, 0)][DBLP] ACRI, 2004, pp:40-49 [Conf]
- Pradipta Maji, Biplab K. Sikdar, Parimal Pal Chaudhuri
Cellular Automata Evolution for Pattern Classification. [Citation Graph (0, 0)][DBLP] ACRI, 2004, pp:660-669 [Conf]
- Chandrama Shaw, Sukanta Das, Biplab K. Sikdar
Cellular Automata Based Encoding Technique for Wavelet Transformed Data Targeting Still Image Compression. [Citation Graph (0, 0)][DBLP] ACRI, 2006, pp:141-146 [Conf]
- Chandrama Shaw, Pradipta Maji, Sourav Saha, Biplab K. Sikdar, Samir Roy, Parimal Pal Chaudhuri
Cellular Automata Based Encompression Technology for Voice Data. [Citation Graph (0, 0)][DBLP] ACRI, 2004, pp:258-267 [Conf]
- Niloy Ganguly, Pradipta Maji, Arijit Das, Biplab K. Sikdar, Parimal Pal Chaudhuri
Characterization of Non-linear Cellular Automata Model for Pattern Recognition. [Citation Graph (0, 0)][DBLP] AFSS, 2002, pp:214-220 [Conf]
- Sukanta Das, Debdas Dey, Subhayan Sen, Biplab K. Sikdar, Parimal Pal Chaudhuri
An efficient design of non-linear CA based PRPG for VLSI circuit testing. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2004, pp:110-112 [Conf]
- Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaudhuri
Design of An On-Chip Test Pattern Generator Without Prohibited Pattern Set (PPS). [Citation Graph (0, 0)][DBLP] ASP-DAC, 2002, pp:689-696 [Conf]
- Samir Roy, Biplab K. Sikdar, Monalisa Mukherjee, Debesh K. Das
Degree-Of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2002, pp:671-676 [Conf]
- Biplab K. Sikdar, Debesh K. Das, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee, Parimal Pal Chaudhuri
Cellular automata as a built in self test structure. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2001, pp:319-324 [Conf]
- Sukanta Das, Hafizur Rahaman, Biplab K. Sikdar
Cost Optimal Design of Nonlinear CA based PRPG for Test Applications. [Citation Graph (0, 0)][DBLP] Asian Test Symposium, 2005, pp:284-287 [Conf]
- Sukanta Das, Biplab K. Sikdar, Parimal Pal Chaudhuri
Nonlinear CA Based Scalable Design of On-Chip TPG for Multiple Cores. [Citation Graph (0, 0)][DBLP] Asian Test Symposium, 2004, pp:331-334 [Conf]
- Sukanta Das, Anirban Kundu, Biplab K. Sikdar
Nonlinear CA Based Design of Test Set Generator Targeting Pseudo-Random Pattern Resistant Faults. [Citation Graph (0, 0)][DBLP] Asian Test Symposium, 2004, pp:196-201 [Conf]
- Sukanta Das, Anirban Kundu, Subhayan Sen, Biplab K. Sikdar, Parimal Pal Chaudhuri
Non-Linear Celluar Automata Based PRPG Design (Without Prohibited Pattern Set) In Linear Time Complexity. [Citation Graph (0, 0)][DBLP] Asian Test Symposium, 2003, pp:78-83 [Conf]
- Niloy Ganguly, Anindyasundar Nandi, Sukanta Das, Biplab K. Sikdar, Parimal Pal Chaudhuri
An Evolutionary Strategy To Design An On-Chip Test Pattern Generator Without Prohibited Pattern Set (PPS). [Citation Graph (0, 0)][DBLP] Asian Test Symposium, 2002, pp:260-265 [Conf]
- Samir Roy, Biplab K. Sikdar
Power Conscious BIST Design for Sequential Circuits Using ghost-FSM. [Citation Graph (0, 0)][DBLP] Asian Test Symposium, 2003, pp:190-195 [Conf]
- Biplab K. Sikdar, Niloy Ganguly, Aniket Karmakar, Subha Sankar Chowdhury, Parimal Pal Chaudhuri
Multiple Attractor Cellular Automata for Hierarchical Diagnosis of VLSI Circuits. [Citation Graph (0, 0)][DBLP] Asian Test Symposium, 2001, pp:385-390 [Conf]
- Biplab K. Sikdar, Samir Roy, Debesh K. Das
Enhancing BIST Quality of Sequential Machines through Degree-of-Freedom Analysis. [Citation Graph (0, 0)][DBLP] Asian Test Symposium, 2001, pp:285-0 [Conf]
- Biplab K. Sikdar, Arijit Sarkar, Samir Roy, Debesh K. Das
Synthesis of Testable Finite State Machine Through Decomposition. [Citation Graph (0, 0)][DBLP] Asian Test Symposium, 2005, pp:398-403 [Conf]
- Niloy Ganguly, Arijit Das, Pradipta Maji, Biplab K. Sikdar, Parimal Pal Chaudhuri
Evolving Cellular Automata Based Associative Memory for Pattern Recognition. [Citation Graph (0, 0)][DBLP] HiPC, 2001, pp:115-124 [Conf]
- Chandrama Shaw, Biplab K. Sikdar, N. C. Maiti
CA Based Document Compression Technology. [Citation Graph (0, 0)][DBLP] ICONIP, 2004, pp:679-685 [Conf]
- Parimal Pal Chaudhuri, Dipanwita Roy Chowdhury, Kolin Paul, Biplab K. Sikdar
Theory and Applications of Cellular Automata for VLSI Design and Testing. [Citation Graph (0, 0)][DBLP] VLSI Design, 2000, pp:4- [Conf]
- Sukanta Das, Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaudhuri
Design Of A Universal BIST (UBIST) Structure. [Citation Graph (0, 0)][DBLP] VLSI Design, 2003, pp:161-166 [Conf]
- Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaudhuri
Design of an On-Chip Test Pattern Generator without Prohibited Pattern Set (PPS). [Citation Graph (0, 0)][DBLP] VLSI Design, 2002, pp:689-0 [Conf]
- Kolin Paul, Ranadeep Ghosal, Biplab K. Sikdar, Santashil Pal Chaudhuri, Dipanwita Roy Chowdhury
GF(2p) CA Based Vector Quantization for Fast Encoding of Still Images. [Citation Graph (0, 0)][DBLP] VLSI Design, 2000, pp:140-143 [Conf]
- Samir Roy, U. Maulik, Biplab K. Sikdar
Exploiting Ghost-FSMs as a BIST Structure for Sequential Machines. [Citation Graph (0, 0)][DBLP] VLSI Design, 2003, pp:155-160 [Conf]
- Samir Roy, Biplab K. Sikdar, Monalisa Mukherjee, Debesh K. Das
Degree-of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area. [Citation Graph (0, 0)][DBLP] VLSI Design, 2002, pp:671-676 [Conf]
- Biplab K. Sikdar, Sukanta Das, Samir Roy, Niloy Ganguly, Debesh K. Das
Cellular Automata Based Test Structures with Logic Folding. [Citation Graph (0, 0)][DBLP] VLSI Design, 2005, pp:71-74 [Conf]
- Biplab K. Sikdar, Purnabha Majumder, Parimal Pal Chaudhuri, Niloy Ganguly
Design Of Multiple Attractor Gf (2p) Cellular AutomataFor Diagnosis Of Vlsi Circuits. [Citation Graph (0, 0)][DBLP] VLSI Design, 2001, pp:454-459 [Conf]
- Biplab K. Sikdar, Purnabha Majumder, Monalisa Mukherjee, Parimal Pal Chaudhuri, Debesh K. Das, Niloy Ganguly
Hierarchical Cellular Automata As An On-Chip Test Pattern Generator. [Citation Graph (0, 0)][DBLP] VLSI Design, 2001, pp:403-0 [Conf]
- Biplab K. Sikdar, Kolin Paul, Gosta Pada Biswas, Parimal Pal Chaudhuri, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee
Theory and Application of GF(2p) Cellular Automata as On-chip Test Pattern Generator. [Citation Graph (0, 0)][DBLP] VLSI Design, 2000, pp:556-561 [Conf]
- H. Rahaman, Jimson Mathew, B. K. Sikdar, Dhiraj K. Pradhan
Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}). [Citation Graph (0, 0)][DBLP] VTS, 2007, pp:422-430 [Conf]
- Pradipta Maji, Chandrama Shaw, Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaudhuri
Theory and Application of Cellular Automata For Pattern Classification. [Citation Graph (0, 0)][DBLP] Fundam. Inform., 2003, v:58, n:2003, pp:321-354 [Journal]
- Niloy Ganguly, Pradipta Maji, Biplab K. Sikdar, Parimal Pal Chaudhuri
Generalized Multiple Attractor Cellular Automata (GMACA) Model for Associative Memory. [Citation Graph (0, 0)][DBLP] IJPRAI, 2002, v:16, n:7, pp:781-796 [Journal]
- Biplab K. Sikdar, Niloy Ganguly, Parimal Pal Chaudhuri
Design of hierarchical cellular automata for on-chip test pattern generator. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:12, pp:1530-1539 [Journal]
- Biplab K. Sikdar, Niloy Ganguly, Parimal Pal Chaudhuri
Generation of test patterns without prohibited pattern set. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:12, pp:1650-1660 [Journal]
- Biplab K. Sikdar, Niloy Ganguly, Parimal Pal Chaudhuri
Fault diagnosis of VLSI circuits with cellular automata based pattern classifier. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:7, pp:1115-1131 [Journal]
- Biplab K. Sikdar, Samir Roy, Debesh K. Das
A Degree-of-Freedom Based Synthesis Scheme for Sequential Machines with Enhanced BIST Quality and Reduced Area. [Citation Graph (0, 0)][DBLP] J. Electronic Testing, 2005, v:21, n:1, pp:83-93 [Journal]
- Sukanta Das, Anirban Kundu, Biplab K. Sikdar, Parimal Pal Chaudhuri
Design of Nonlinear CA Based TPG Without Prohibited Pattern Set In Linear Time. [Citation Graph (0, 0)][DBLP] J. Electronic Testing, 2005, v:21, n:1, pp:95-107 [Journal]
Characterization of Non-reachable States in Irreversible CAState Space. [Citation Graph (, )][DBLP]
Exploring CAState Space to Synthesize Cellular Automata with Specified Attractor Set. [Citation Graph (, )][DBLP]
Characterization of CA Rules for SACA Targeting Detection of Faulty Nodes in WSN. [Citation Graph (, )][DBLP]
Programmable Cellular Automata (PCA) Based Advanced Encryption Standard (AES) Hardware Architecture. [Citation Graph (, )][DBLP]
CA Based Built-In Self-Test Structure for SoC. [Citation Graph (, )][DBLP]
CA Rules Identification for Efficient Design of Pattern Classifier. [Citation Graph (, )][DBLP]
CA Based Data Servicing In Cellular Mobile Network. [Citation Graph (, )][DBLP]
Cellular Automata Model for Cost Optimal Design of Steel Building Frames. [Citation Graph (, )][DBLP]
Characterization of 1-d Periodic Boundary Reversible CA. [Citation Graph (, )][DBLP]
Characterization of Single Cycle CA and its Application in Pattern Classification. [Citation Graph (, )][DBLP]
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