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Dipanwita Roy Chowdhury: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Debojyoti Bhattacharya, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury
    A Cellular Automata Based Approach for Generation of Large Primitive Polynomial and Its Application to RS-Coded MPSK Modulation. [Citation Graph (0, 0)][DBLP]
    ACRI, 2006, pp:204-214 [Conf]
  2. Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury
    Characterization of a Class of Complemented Group Cellular Automata. [Citation Graph (0, 0)][DBLP]
    ACRI, 2004, pp:775-784 [Conf]
  3. Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury
    Generation of Expander Graphs Using Cellular Automata and Its Applications to Cryptography. [Citation Graph (0, 0)][DBLP]
    ACRI, 2006, pp:636-645 [Conf]
  4. Pallavi Joshi, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury
    Design and Analysis of a Robust and Efficient Block Cipher using Cellular Automata. [Citation Graph (0, 0)][DBLP]
    AINA (2), 2006, pp:67-71 [Conf]
  5. Subhayu Basu, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury, Indranil Sengupta, Sudipta Bhawmik
    Reformatting Test Patterns for Testing Embedded Core Based System Using Test Access Mechanism (TAM) Switch. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:598-603 [Conf]
  6. Debdeep Mukhopadhyay, Shibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya
    CryptoScan: A Secured Scan Chain Architecture. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:348-353 [Conf]
  7. Kundan Kumar, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury
    A Programmable Parallel Structure to perform Galois Field Exponentiation. [Citation Graph (0, 0)][DBLP]
    ICIT, 2006, pp:277-280 [Conf]
  8. Shibaji Banerjee, Dipanwita Roy Chowdhury
    Built-In Self-Test for Flash Memory Embedded in SoC. [Citation Graph (0, 0)][DBLP]
    DELTA, 2006, pp:379-384 [Conf]
  9. Kolin Paul, Dipanwita Roy Chowdhury, Parimal Pal Chaudhuri
    Cellular Automata Based Transform Coding for Image Compression. [Citation Graph (0, 0)][DBLP]
    HiPC, 1999, pp:269-273 [Conf]
  10. Dipanwita Roy Chowdhury, Supratik Chakraborty, B. Vamsi, B. Pal Chaudhuri
    Cellular automata based synthesis of easily and fully testable FSMs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:650-653 [Conf]
  11. Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury
    Cellular Automata : An Ideal Candidate for a Block Cipher. [Citation Graph (0, 0)][DBLP]
    ICDCIT, 2004, pp:452-457 [Conf]
  12. Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury
    Cellular automata based key agreement. [Citation Graph (0, 0)][DBLP]
    ICETE, 2005, pp:262-267 [Conf]
  13. Subhayan Sen, Chandrama Shaw, Dipanwita Roy Chowdhury, Niloy Ganguly, Parimal Pal Chaudhuri
    Cellular Automata Based Cryptosystem (CAC). [Citation Graph (0, 0)][DBLP]
    ICICS, 2002, pp:303-314 [Conf]
  14. Roshni Chatterjee, Moiz A. Saifee, Dipanwita Roy Chowdhury
    Modifications of SHA-0 to Prevent Attacks. [Citation Graph (0, 0)][DBLP]
    ICISS, 2005, pp:277-289 [Conf]
  15. Debdeep Mukhopadhyay, Abhishek Chaudhary, Arvind Nebhnani, Dipanwita Roy Chowdhury
    CCMEA: Customized Cellular Message Encryption Algorithm for Wireless Networks. [Citation Graph (0, 0)][DBLP]
    ICISS, 2005, pp:217-227 [Conf]
  16. Mounita Saha, Dipanwita Roy Chowdhury
    Design of Key Establishment Protocol Using One-Way Functions to Avert insider-replay Attack. [Citation Graph (0, 0)][DBLP]
    ICISS, 2006, pp:194-204 [Conf]
  17. Debabrata Bagchi, Dipanwita Roy Chowdhury, Joy Mukherjee, Santanu Chattopadhyay
    A Novel Strategy to Test Core Based Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:122-127 [Conf]
  18. Shibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya
    An Efficient Scan Tree Design for Compact Test Pattern Set. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:175-180 [Conf]
  19. Shibaji Banerjee, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury
    Computer Aided Test (CAT) Tool for Mixed Signal SOCs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:787-790 [Conf]
  20. Subhayu Basu, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury, Indranil Sengupta, Sudipta Bhawmik
    Reformatting Test Patterns for Testing Embedded Core Based System Using Test Access Mechanism (TAM) Switch. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:598-603 [Conf]
  21. Santanu Chattopadhyay, Dipanwita Roy Chowdhury, Subarna Bhattacharjee, Parimal Pal Chaudhuri
    Board level fault diagnosis using cellular automata array. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:343-348 [Conf]
  22. Parimal Pal Chaudhuri, Dipanwita Roy Chowdhury, Kolin Paul, Biplab K. Sikdar
    Theory and Applications of Cellular Automata for VLSI Design and Testing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:4- [Conf]
  23. Dipanwita Roy Chowdhury, Parimal Pal Chaudhuri
    Architecture for VLSI Design of CA Based Byte Error Correcting Code Decoders. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:283-286 [Conf]
  24. Dipanwita Roy Chowdhury, Supratik Chakraborty, Parimal Pal Chaudhuri
    Synthesis of Self-Checking Sequential Machines Using Cellular Automata. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:107- [Conf]
  25. Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury
    An Efficient End to End Design of Rijndael Cryptosystem in 0.18 ? CMOS. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:405-410 [Conf]
  26. Kolin Paul, Dipanwita Roy Chowdhury
    Application of GF(2p) CA in Burst Error Correcting Codes. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:562-567 [Conf]
  27. Kolin Paul, Parimal Pal Chaudhuri, Dipanwita Roy Chowdhury
    Scalable Pipelined Micro-Architecture for Wavelet Transform. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:144-0 [Conf]
  28. Kolin Paul, P. Dutta, Dipanwita Roy Chowdhury, Prasanta Kumar Nandi, Parimal Pal Chaudhuri
    A VLSI Architecture for On-Line Image Decompression Using GF(28) Cellular Automata. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:532-537 [Conf]
  29. Kolin Paul, Ranadeep Ghosal, Biplab K. Sikdar, Santashil Pal Chaudhuri, Dipanwita Roy Chowdhury
    GF(2p) CA Based Vector Quantization for Fast Encoding of Still Images. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:140-143 [Conf]
  30. Subhayan Sen, Sk. Iqbal Hossain, Kabirul Islam, Dipanwita Roy Chowdhury, Parimal Pal Chaudhuri
    Cryptosystem Designed for Embedded System Security. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:271-276 [Conf]
  31. Debdeep Mukhopadhyay, Pallavi Joshi, Dipanwita Roy Chowdhury
    An Efficient Design of Cellular Automata Based Cryptographically Robust One-Way Function. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:842-853 [Conf]
  32. Dipanwita Roy Chowdhury, P. Subbarao, Parimal Pal Chaudhuri
    Characterization of two-dimensional cellular automata using matrix algebra. [Citation Graph (0, 0)][DBLP]
    Inf. Sci., 1993, v:71, n:3, pp:289-314 [Journal]
  33. Suraj Peri, J. Daniel Navarro, Troels Z. Kristiansen, Ramars Amanchy, Vineeth Surendranath, Babylakshmi Muthusamy, T. K. B. Gandhi, K. N. Chandrika, Nandan Deshpande, Shubha Suresh, B. P. Rashmi, K. Shanker, N. Padma, Vidya Niranjan, H. C. Harsha, Naveen Talreja, B. M. Vrushabendra, M. A. Ramya, A. J. Yatish, Mary Joy, H. N. Shivashankar, M. P. Kavitha, Minal Menezes, Dipanwita Roy Chowdhury, Neelanjana Ghosh, R. Saravana, Sreenath Chandran, Sujatha Mohan, Chandra Kiran Jonnalagadda, C. K. Prasad, Chandan Kumar-Sinha, Krishna S. Deshpande, Akhilesh Pandey
    Human protein reference database as a discovery resource for proteomics. [Citation Graph (0, 0)][DBLP]
    Nucleic Acids Research, 2004, v:32, n:Database-Issue, pp:497-501 [Journal]
  34. Supratik Chakraborty, Dipanwita Roy Chowdhury, Parimal Pal Chaudhuri
    Theory and Application of Nongroup Cellular Automata for Synthesis of Easily Testable Finite State Machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:7, pp:769-781 [Journal]
  35. Santanu Chattopadhyay, Dipanwita Roy Chowdhury, Subarna Bhattacharjee, Parimal Pal Chaudhuri
    Cellular-Automata-Array-Based Diagnosis of Board Level Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:8, pp:817-828 [Journal]
  36. Dipanwita Roy Chowdhury, Idranil Sen Gupta, Parimal Pal Chaudhuri
    A Low-Cost High-Capacity Associative Memory Design Using Cellular Automata. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:10, pp:1260-1264 [Journal]
  37. Dipanwita Roy Chowdhury, Indranil Sengupta, Parimal Pal Chaudhuri
    CA-Based Byte Error-Correcting Code. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:3, pp:371-382 [Journal]
  38. Dipanwita Roy Chowdhury, Saugata Basu, Idranil Sen Gupta, Parimal Pal Chaudhuri
    Design of CAECC-Cellular Automata Based Error Correcting Code. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:6, pp:759-764 [Journal]
  39. Kolin Paul, Dipanwita Roy Chowdhury, Parimal Pal Chaudhuri
    Theory of Extended Linear Machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:9, pp:1106-1110 [Journal]
  40. Debojyoti Bhattacharya, Debdeep Mukhopadhyay, Dhiman Saha, Dipanwita Roy Chowdhury
    Strengthening NLS Against Crossword Puzzle Attack. [Citation Graph (0, 0)][DBLP]
    ACISP, 2007, pp:29-44 [Conf]
  41. Monjur Alam, Sonai Ray, Debdeep Mukhopadhyay, Santosh Ghosh, Dipanwita Roy Chowdhury, Indranil Sengupta
    An area optimized reconfigurable encryptor for AES-Rijndael. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1116-1121 [Conf]

  42. An Efficient n×nBoolean Mapping Using Additive Cellular Automata. [Citation Graph (, )][DBLP]


  43. An Improved Double Byte Error Correcting Code Using Cellular Automata. [Citation Graph (, )][DBLP]


  44. coreBIST: A Cellular Automata Based Core for Self Testing System-on-Chips. [Citation Graph (, )][DBLP]


  45. Theory of Composing Non-linear Machines with Predictable Cyclic Structures. [Citation Graph (, )][DBLP]


  46. d-Monomial Tests of Nonlinear Cellular Automata for Cryptographic Design. [Citation Graph (, )][DBLP]


  47. Generating Cryptographically Suitable Non-linear Maximum Length Cellular Automata. [Citation Graph (, )][DBLP]


  48. Null Boundary 90/150 Cellular Automata for Multi-byte Error Correcting Code. [Citation Graph (, )][DBLP]


  49. A Novel Seed Selection Algorithm for Test Time Reduction in BIST. [Citation Graph (, )][DBLP]


  50. A secure verifiable key agreement protocol for mobile conferencing. [Citation Graph (, )][DBLP]


  51. A Robust GF(p) Parallel Arithmetic Unit for Public Key Cryptography. [Citation Graph (, )][DBLP]


  52. A GF(p) elliptic curve group operator resistant against side channel attacks. [Citation Graph (, )][DBLP]


  53. A Near Optimal S-Box Design. [Citation Graph (, )][DBLP]


  54. Design of a Differential Power Analysis Resistant Masked AES S-Box. [Citation Graph (, )][DBLP]


  55. Raising the Level of Abstraction for the Timing Verification of System-on-Chips. [Citation Graph (, )][DBLP]


  56. Nmix: An Ideal Candidate for Key Mixing. [Citation Graph (, )][DBLP]


  57. An Efficient Group Key Agreement Protocol for Heterogeneous Environment. [Citation Graph (, )][DBLP]


  58. A New Image Encryption Algorithm using Cellular Automata. [Citation Graph (, )][DBLP]


  59. Single Chip Encryptor/Decryptor Core Implementation of AES Algorithm. [Citation Graph (, )][DBLP]


  60. A Secure and Efficient Protocol for Group Key agreement in Heterogeneous Environment [Citation Graph (, )][DBLP]


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