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Jiun-In Guo: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Tai-Lun Chang, Ying-Ming Tsai, Chih-Da Chien, Chien-Chang Lin, Jiun-In Guo
    A high-performance MPEG4 bitstream processing core. [Citation Graph (0, 0)][DBLP]
    ICME, 2004, pp:467-470 [Conf]
  2. Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh
    A power-aware SNR-progressive DCT/IDCT IP core design for multimedia transform coding. [Citation Graph (0, 0)][DBLP]
    ICME, 2004, pp:1683-1686 [Conf]
  3. Hsiu-Cheng Chang, Chien-Chang Lin, Jiun-In Guo
    A novel low-cost high-performance VLSI architecture for MPEG-4 AVC/H.264 CAVLC decoding. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6110-6113 [Conf]
  4. Hun-Chen Chen, Jiun-In Guo, Chein-Wei Jen
    A memory efficient realization of cyclic convolution and its application to discrete cosine transform. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:33-36 [Conf]
  5. Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang
    An efficient direct 2-D transform coding IP design for MPEG-4 AVC/H.264. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4517-4520 [Conf]
  6. Chih-Da Chien, Ho-Chun Chen, Lin-Chieh Huang, Jiun-In Guo
    A low-power motion compensation IP core design for MPEG-1/2/4 video decoding. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4542-4545 [Conf]
  7. Chih-Da Chien, Chien-Chang Lin, Jiun-In Guo, Tien-Fu Chen
    A power-aware IP core generator for the one-dimensional discrete Fourier transform. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2004, pp:637-640 [Conf]
  8. Jiun-In Guo, Jia-Wei Chen, Han-Chen Chen
    A new 2-D 8/spl times/8 DCT/IDT core design using group distributed arithmetic. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:752-755 [Conf]
  9. Jiun-In Guo, Chih-Da Chien, Chien-Chang Lin
    A parameterized low power design for the variable-length discrete Fourier transform using dynamic pipelining. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:293-296 [Conf]
  10. Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen
    A CORDIC-based VLSI Array for Computing 2-D Discrete Hartley Transform. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1571-1574 [Conf]
  11. Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen
    A General Approach to Design VLSI Arrays for the Multi-dimensional Discrete Hartley Transform. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:235-238 [Conf]
  12. Yu-Sheng Lin, Jiun-In Guo, C. Bernard Shung, Chein-Wei Jen
    A Multi-phase Shared Bus Structure for the Fast Fourier Transform. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1575-1578 [Conf]
  13. Jiun-In Guo
    A low cost 2-D inverse discrete cosine transform design for image compression. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:658-661 [Conf]
  14. Jiun-In Guo
    A new DA-based array for one dimensional discrete Hartley transform. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:662-665 [Conf]
  15. Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh, Tien-Fu Chen
    A power-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:141-144 [Conf]
  16. Rei-Chin Ju, Jia-Wei Chen, Jiun-In Guo, Tien-Fu Chen
    A parameterized power-aware IP core generator for the 2-D 8×8 DCT/IDCT. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:769-772 [Conf]
  17. Hun-Chen Chen, Jiun-In Guo, Chein-Wei Jen
    A new group distributed arithmetic design for the one dimensional discrete Fourier transform. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:421-424 [Conf]
  18. Jui-Cheng Yen, Jiun-In Guo
    Design of a new signal security system. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:121-124 [Conf]
  19. Jiun-In Guo, Chien-Chang Lin
    A new hardware efficient design for the one dimensional discrete Fourier transform. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:549-552 [Conf]
  20. Kuan-Hung Chen, Kuo-Chuan Chao, Jinn-Shyan Wang, Yuan-Sun Chu, Jiun-In Guo
    An efficient spurious power suppression technique (SPST) and its applications on MPEG-4 AVC/H.264 transform coding design. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:155-160 [Conf]
  21. Hun-Chen Chen, Jui-Cheng Yen, Jiun-In Guo
    Design of a New Cryptography System. [Citation Graph (0, 0)][DBLP]
    IEEE Pacific Rim Conference on Multimedia, 2002, pp:1041-1048 [Conf]
  22. Jiun-In Guo, Chien-Chang Lin, Chih-Da Chien
    A Low-Power Parameterized Hardware Design for the One-Dimensional Discrete Fourier Transform of Variable Lengths. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2002, v:11, n:4, pp:405-428 [Journal]
  23. Hun-Chen Chen, Jiun-In Guo, Tian-Sheuan Chang, Chein-Wei Jen
    A memory-efficient realization of cyclic convolution and its application to discrete cosine transform. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2005, v:15, n:3, pp:445-453 [Journal]
  24. Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang
    A high-performance direct 2-D transform coding IP design for MPEG-4AVC/H.264. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2006, v:16, n:4, pp:472-483 [Journal]
  25. Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh, Jia-Wei Chen
    An Energy-Aware IP Core Design for the Variable-Length DCT/IDCT Targeting at MPEG4 Shape-Adaptive Transforms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2005, v:15, n:5, pp:704-715 [Journal]
  26. Jiun-In Guo, Rei-Chin Ju, Jia-Wei Chen
    An efficient 2-D DCT/IDCT core design using cyclic convolution and adder-based realization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2004, v:14, n:4, pp:416-428 [Journal]
  27. Jiun-In Guo, Chih-Chen Li
    A generalized architecture for the one-dimensional discrete cosine and sine transforms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2001, v:11, n:7, pp:874-881 [Journal]
  28. Jui-Chin Chu, Wei-Chun Ku, Shu-Hsuan Chou, Tien-Fu Chen, Jiun-In Guo
    An Embedded Coherent-Multithreading Multimedia Processor and Its Programming Model. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:652-657 [Conf]
  29. Guo-An Jian, Chih-Da Chien, Jiun-In Guo
    A Memory-Based Hardware Accelerator for Real-Time MPEG-4 Audio Coding and Reverberation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1569-1572 [Conf]
  30. Kuan-Hung Chen, Yuan-Sun Chu, Yu-Min Chen, Jiun-In Guo
    A High-Speed/Low-Power Multiplier Using an Advanced Spurious Power Suppression Technique. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3139-3142 [Conf]
  31. Jia-Wei Chen, Kuan-Hung Chen, Jinn-Shyan Wang, Jiun-In Guo
    A performance-aware IP core design for multimode transform coding using scalable-DA algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  32. Kuo-Chuan Chao, Kuan-Hung Chen, Yuan-Sun Chu, Jiun-In Guo
    Low-power mechanism with power block management. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  33. Jui-Chin Chu, Chih-Wen Huang, He-Chun Chen, Keng-Po Lu, Ming-Shuan Lee, Jiun-In Guo, Tien-Fu Chen
    Design of customized functional units for the VLIW-based multi-threading processor core targeted at multimedia applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  34. Chih-Da Chien, Keng-Po Lu, Yi-Hung Shih, Jiun-In Guo
    A high performance CAVLC encoder design for MPEG-4 AVC/H.264 video coding applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  35. A dynamic quality-scalable H.264 video encoder chip. [Citation Graph (, )][DBLP]


  36. CKVdd: a self-stabilization ramp-vdd technique for dynamic power reduction. [Citation Graph (, )][DBLP]


  37. A High Throughput VLSI Architecture Design for H.264 Context-Based Adaptive Binary Arithmetic Decoding with Look Ahead Parsing. [Citation Graph (, )][DBLP]


  38. A Condition-based Intra Prediction Algorithm for H.264/AVC. [Citation Graph (, )][DBLP]


  39. Collaborative Multithreading: An Open Scalable Processor Architecture for Embedded Multimedia Applications. [Citation Graph (, )][DBLP]


  40. A Low Latency Memory Controller for Video Coding Systems. [Citation Graph (, )][DBLP]


  41. Low Complexity Multi-Standard Video Player for Portable Multimedia Applications. [Citation Graph (, )][DBLP]


  42. Low complexity fractional motion estimation with adaptive mode selection for H.264/AVC. [Citation Graph (, )][DBLP]


  43. A remote thin client system for real time multimedia streaming over VNC. [Citation Graph (, )][DBLP]


  44. A Low Complexity Error Concealment Method for H.264 Video Coding Facilitating Hardware Realization. [Citation Graph (, )][DBLP]


  45. Optimization of VC-1/H.264/AVS Video Decoders on Embedded Processors. [Citation Graph (, )][DBLP]


  46. A Low Complexity High Quality Interger Motion Estimation Architecture Design for H.264/AVC. [Citation Graph (, )][DBLP]


  47. Predictive Mode Searching Policy for H.264/AVC Intra Prediction. [Citation Graph (, )][DBLP]


  48. Low Complexity High Quality Fractional Motion Estimation Algorithm and Architecture Design for H.264/AVC. [Citation Graph (, )][DBLP]


  49. A Quality Scalable H.264/AVC Baseline Intra Encoder for High Definition Video Applicaitons. [Citation Graph (, )][DBLP]


  50. Joint algorithm/code-level optimization of H.264 video decoder for mobile multimedia applications. [Citation Graph (, )][DBLP]


  51. A H.264 basic-unit level rate control algorithm facilitating hardware realization. [Citation Graph (, )][DBLP]


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