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Chien-Ming Wu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Lan-Da Van, Hsin-Fu Luo, Chien-Ming Wu, Wen-Hsiang Hu, Chun-Ming Huang, Wei-Chang Tsai
    A high-performance area-aware DSP processor architecture for video codecs. [Citation Graph (0, 0)][DBLP]
    ICME, 2004, pp:1499-1502 [Conf]
  2. Jun-Hong Chen, Ming-Der Shieh, Chien-Ming Wu
    Concurrent algorithm for high-speed point multiplication in elliptic curve cryptography. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5254-5257 [Conf]
  3. Chien-Ming Wu, Ming-Der Shieh, Hsin-Fu Lo, Min-Hsiung Hu
    Implementation of channel demodulator for DAB system. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:137-140 [Conf]
  4. Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang
    Systolic VLSI realization of a novel iterative division algorithm over GF(2m): a high-speed, low-complexity design. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:33-36 [Conf]
  5. Hsin-Fu Lo, Ming-Der Shieh, Chien-Ming Wu
    Design of an efficient FFT processor for DAB system. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:654-657 [Conf]
  6. Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu
    VLSI architecture of extended in-place path metric update for Viterbi decoders. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:206-209 [Conf]
  7. Jin-Chuan Huang, Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu
    An area-efficient versatile Reed-Solomon decoder for ADSL. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:517-520 [Conf]
  8. Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Yin-Tsung Hwang, Jun-Hong Chen, Hsin-Fu Lo
    VLSI architecture exploration for sliding-window Log-MAP decoders. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:513-516 [Conf]
  9. Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu
    Memory arrangements in turbo decoders using sliding-window BCJR algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:557-560 [Conf]
  10. Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang
    An area-efficient systolic division circuit over GF(2/sup m/) for secure communication. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:733-736 [Conf]
  11. Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang
    High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m). [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:3, pp:375-380 [Journal]
  12. Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Yin-Tsung Hwang, Jun-Hong Chen
    VLSI architectural design tradeoffs for sliding-window log-MAP decoders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:4, pp:439-447 [Journal]
  13. Ming-Der Shieh, Tai-Ping Wang, Chien-Ming Wu, Chun-Ming Huang
    Efficient path metric access for reducing interconnect overhead in Viterbi decoders. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  14. High-performance low-complexity bit-plane coding scheme for MPEG-4 FGS. [Citation Graph (, )][DBLP]


  15. PrSoC: Programmable System-on-chip (SoC) for silicon prototyping. [Citation Graph (, )][DBLP]


  16. True Event Decision by Cooperative Sensor Network. [Citation Graph (, )][DBLP]


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