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Srinivas Devadas: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Blaise Gassend, Dwaine E. Clarke, Marten van Dijk, Srinivas Devadas
    Controlled Physical Random Functions. [Citation Graph (0, 0)][DBLP]
    ACSAC, 2002, pp:149-160 [Conf]
  2. Stan Y. Liao, Srinivas Devadas, Kurt Keutzer
    Code density optimization for embedded DSP processors using data compression techniques. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1995, pp:272-285 [Conf]
  3. José Monteiro, John Rinderknecht, Srinivas Devadas, Abhijit Ghosh
    Optimization of combinational and sequential logic circuits for low power using precomputation. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1995, pp:430-444 [Conf]
  4. Dwaine E. Clarke, Srinivas Devadas, Marten van Dijk, Blaise Gassend, G. Edward Suh
    Incremental Multiset Hash Functions and Their Application to Memory Integrity Checking. [Citation Graph (0, 0)][DBLP]
    ASIACRYPT, 2003, pp:188-207 [Conf]
  5. G. Edward Suh, Jae W. Lee, David Zhang, Srinivas Devadas
    Secure program execution via dynamic information flow tracking. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2004, pp:85-96 [Conf]
  6. Blaise Gassend, Dwaine E. Clarke, Marten van Dijk, Srinivas Devadas
    Silicon physical random functions. [Citation Graph (0, 0)][DBLP]
    ACM Conference on Computer and Communications Security, 2002, pp:148-160 [Conf]
  7. Pranav Ashar, Srinivas Devadas, A. Richard Newton
    A Unified Approach to the Decomposition and Re-Decomposition of Sequential Machines. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:601-606 [Conf]
  8. Vishal Bhagwati, Srinivas Devadas
    Automatic Verification of Pipelined Microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:603-608 [Conf]
  9. Douglas Braun, Jeffrey L. Burns, Srinivas Devadas, Hi-Keung Tony Ma, Kartikeya Mayaram, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli
    Chameleon: a new multi-layer channel router. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:495-502 [Conf]
  10. Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer
    Robust Delay-Fault Test Generation and Synthesis for Testability Under A Standard Scan Design Methodology. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:80-86 [Conf]
  11. Derek Chiou, Prabhat Jain, Larry Rudolph, Srinivas Devadas
    Application-specific memory management for embedded systems using software-controlled caches. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:416-419 [Conf]
  12. Srinivas Devadas
    Approaches to Multi-level Sequential Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:270-276 [Conf]
  13. Srinivas Devadas
    General Decomposition of Sequential Machines: Relationships to State Assignment. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:314-320 [Conf]
  14. Srinivas Devadas, Kurt Keutzer
    Synthesis and Optimization Procedures for Robustly Delay-Fault Testable Combinational Logic Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:221-227 [Conf]
  15. Srinivas Devadas, Kurt Keutzer, Sharad Malik
    A Synthesis-Based Test Generation and Compaction Algorithm for Multifaults. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:359-365 [Conf]
  16. Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang
    Certified Timing Verification and the Transition Delay of a Logic Circuit. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:549-555 [Conf]
  17. Srinivas Devadas, Sharad Malik
    A Survey of Optimization Techniques Targeting Low Power VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:242-247 [Conf]
  18. Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton
    On the Verification of Sequential Machines at Differing Levels of Abstraction. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:271-276 [Conf]
  19. Srinivas Devadas, A. Richard Newton
    GENIE: a generalized array optimizer for VLSI synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:631-637 [Conf]
  20. Farzan Fallah, Pranav Ashar, Srinivas Devadas
    Simulation Vector Generation from HDL Descriptions for Observability-Enhanced Statement Coverage. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:666-671 [Conf]
  21. Farzan Fallah, Srinivas Devadas, Kurt Keutzer
    Functional Vector Generation for HDL Models Using Linear Programming and 3-Satisfiability. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:528-533 [Conf]
  22. Farzan Fallah, Srinivas Devadas, Kurt Keutzer
    OCCOM: Efficient Computation of Observability-Based Code Coverage Metrics for Functional Verification. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:152-157 [Conf]
  23. Abhijit Ghosh, Srinivas Devadas, Kurt Keutzer, Jacob White
    Estimation of Average Switching Activity in Combinational and Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:253-259 [Conf]
  24. Abhijit Ghosh, Srinivas Devadas, A. Richard Newton
    Verification of Interacting Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:213-219 [Conf]
  25. Abhijit Ghosh, Srinivas Devadas, A. Richard Newton
    Sequential Test Generation at the Register-Transfer and Logic Levels. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:580-586 [Conf]
  26. George Hadjiyiannis, Silvina Hanono, Srinivas Devadas
    ISDL: An Instruction Set Description Language for Retargetability. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:299-302 [Conf]
  27. George Hadjiyiannis, Pietro Russo, Srinivas Devadas
    A Methodology for Accurate Performance Evaluation in Architecture Exploration. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:927-932 [Conf]
  28. Silvina Hanono, Srinivas Devadas
    Instruction Selection, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:510-515 [Conf]
  29. Prabhat Jain, G. Edward Suh, Srinivas Devadas
    Embedded intelligent SRAM. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:869-874 [Conf]
  30. Stan Y. Liao, Srinivas Devadas
    Solving Covering Problems Using LPR-Based Lower Bounds. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:117-120 [Conf]
  31. Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang, Albert Wang
    Code Optimization Techniques for Embedded DSP Microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:599-604 [Conf]
  32. Hi-Keung Tony Ma, Srinivas Devadas, Alberto L. Sangiovanni-Vincentelli, R. Wei
    Logic Verification Algorithms and Their Parallel Implementation. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:283-290 [Conf]
  33. José Monteiro, Srinivas Devadas, Pranav Ashar, Ashutosh Mauskar
    Scheduling Techniques to Enable Power Management. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:349-352 [Conf]
  34. José C. Monteiro, Srinivas Devadas, Bill Lin
    A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:12-17 [Conf]
  35. Ashok Sudarsanam, Stan Y. Liao, Srinivas Devadas
    Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:287-292 [Conf]
  36. Guido Araujo, Srinivas Devadas, Kurt Keutzer, Stan Y. Liao, Sharad Malik, Ashok Sudarsanam, Steven W. K. Tjiang, Albert Wang
    Challenges in code generation for embedded processors. [Citation Graph (0, 0)][DBLP]
    Code Generation for Embedded Processors, 1994, pp:48-64 [Conf]
  37. Blaise Gassend, G. Edward Suh, Dwaine E. Clarke, Marten van Dijk, Srinivas Devadas
    Caches and Hash Trees for Efficient Memory Integrity. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:295-306 [Conf]
  38. G. Edward Suh, Srinivas Devadas, Larry Rudolph
    A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:117-0 [Conf]
  39. Filip Van Aelten, Jonathan Allen, Srinivas Devadas
    Verification of Relations Between Synchronous Machines. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:380-383 [Conf]
  40. Filip Van Aelten, Stan Y. Liao, Jonathan Allen, Srinivas Devadas
    Automatic generation and verification of sufficient correctness properties for synchronous processors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:183-187 [Conf]
  41. Mazhar Alidina, José C. Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou
    Precomputation-based sequential logic optimization for low power. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:74-81 [Conf]
  42. Pranav Ashar, Abhijit Ghosh, Srinivas Devadas, A. Richard Newton
    Implicit State Transition Graphs: Applications to Sequential Logic Synthesis and Test. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:84-87 [Conf]
  43. Michael J. Bryan, Srinivas Devadas, Kurt Keutzer
    Testability-Preserving Circuit Transformations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:456-459 [Conf]
  44. José C. Costa, Srinivas Devadas, José Monteiro
    Observability Analysis of Embedded Software for Coverage-Directed Validation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:27-32 [Conf]
  45. Srinivas Devadas, Abhijit Ghosh, Kurt Keutzer
    An observability-based code coverage metric for functional simulation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:418-425 [Conf]
  46. Srinivas Devadas, Kurt Keutzer
    An Automata-Theoretic Approach to Behavioral Equivalence. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:30-33 [Conf]
  47. Srinivas Devadas, Kurt Keutzer, Sharad Malik
    Delay Computation in Combinational Logic Circuits: Theory and Algorithms. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:176-179 [Conf]
  48. Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang
    Verification of asynchronous interface circuits with bounded wire delays. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:188-195 [Conf]
  49. Prabhat Jain, Srinivas Devadas, Daniel W. Engels, Larry Rudolph
    Software-Assisted Cache Replacement Mechanisms for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:119-126 [Conf]
  50. James H. Kukula, Srinivas Devadas
    Finite State Machine Decomposition by Transition Pairing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:414-417 [Conf]
  51. Stan Y. Liao, Srinivas Devadas, Abhijit Ghosh
    Boolean factorization using multiple-valued minimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:606-611 [Conf]
  52. Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang
    Instruction selection using binate covering for code size optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:393-399 [Conf]
  53. Bill Lin, Srinivas Devadas
    Synthesis of hazard-free multi-level logic under multiple-input changes from binary decision diagrams. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:542-549 [Conf]
  54. José C. Monteiro, Srinivas Devadas, Abhijit Ghosh
    Retiming sequential circuits for low power. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:398-402 [Conf]
  55. Amelia Shen, Srinivas Devadas, Abhijit Ghosh
    Probabilistic construction and manipulation of free Boolean diagrams. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:544-583 [Conf]
  56. Amelia Shen, Abhijit Ghosh, Srinivas Devadas, Kurt Keutzer
    On average power dissipation and random pattern testability of CMOS combinational logic networks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:402-407 [Conf]
  57. Kenneth Y. Yun, Bill Lin, David L. Dill, Srinivas Devadas
    Performance-driven synthesis of asynchronous controllers. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:550-557 [Conf]
  58. Pranav Ashar, Abhijit Ghosh, Srinivas Devadas
    Boolean Satisfiability and Equivalence Checking Using General Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:259-264 [Conf]
  59. Srinivas Devadas, Horng-Fei Jyu, Kurt Keutzer, Sharad Malik
    Statistical Timing Analysis of Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:38-43 [Conf]
  60. Srinivas Devadas, Kurt Keutzer, A. S. Krishnakumar
    Design Verfication and Reachability Analysis Using Algebraic Manipulation. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:250-258 [Conf]
  61. G. Edward Suh, Dwaine E. Clarke, Blaise Gassend, Marten van Dijk, Srinivas Devadas
    AEGIS: architecture for tamper-evident and tamper-resistant processing. [Citation Graph (0, 0)][DBLP]
    ICS, 2003, pp:160-171 [Conf]
  62. G. Edward Suh, Srinivas Devadas, Larry Rudolph
    Analytical cache models with applications to cache partitioning. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:1-12 [Conf]
  63. Hari Balakrishnan, Srinivas Devadas, Douglas Ehlert, Arvind
    Rate Guarantees and Overload Protection in Input-Queued Switches. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 2004, pp:- [Conf]
  64. G. Edward Suh, Charles W. O'Donnell, Ishan Sachdev, Srinivas Devadas
    Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:25-36 [Conf]
  65. José C. Costa, José C. Monteiro, Srinivas Devadas
    Switching activity estimation using limited depth reconvergent path analysis. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:184-189 [Conf]
  66. José Monteiro, Srinivas Devadas
    Techniques for the power estimation of sequential logic circuits under user-specified input sequences and programs. [Citation Graph (0, 0)][DBLP]
    ISLPD, 1995, pp:33-38 [Conf]
  67. Srinivas Devadas
    Minimization of Functions with Multiple-Valued Outputs: Theory and Applications. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1990, pp:308-315 [Conf]
  68. Pranav Ashar, Srinivas Devadas, Kurt Keutzer
    Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:887-896 [Conf]
  69. Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer
    A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:403-410 [Conf]
  70. Srinivas Devadas
    Delay Test Generation for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:144-152 [Conf]
  71. Srinivas Devadas, Kurt Keutzer
    An algorithmic approach to optimizing fault coverage for BIST logic synthesis. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:164-0 [Conf]
  72. Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton
    Redundancies and Don't Cares in Sequential Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:491-500 [Conf]
  73. Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
    Synthesis and Optimization Procedures for Fully and Easily Testable Sequential Machines. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:621-630 [Conf]
  74. Hi-Keung Tony Ma, A. Richard Newton, Srinivas Devadas, Alberto L. Sangiovanni-Vincentelli
    An Incomplete Scan Design Approach to Test Generation for Sequential Machines. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:730-734 [Conf]
  75. G. Edward Suh, Larry Rudolph, Srinivas Devadas
    Effects of Memory Performance on Parallel Job Scheduling. [Citation Graph (0, 0)][DBLP]
    JSSPP, 2001, pp:116-132 [Conf]
  76. G. Edward Suh, Dwaine E. Clarke, Blaise Gassend, Marten van Dijk, Srinivas Devadas
    Efficient Memory Integrity Verification and Encryption for Secure Processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2003, pp:339-350 [Conf]
  77. Dwaine E. Clarke, Blaise Gassend, Thomas Kotwal, Matt Burnside, Marten van Dijk, Srinivas Devadas, Ronald L. Rivest
    The Untrusted Computer Problem and Camera-Based Authentication. [Citation Graph (0, 0)][DBLP]
    Pervasive, 2002, pp:114-124 [Conf]
  78. Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang, Albert Wang
    Storage Assignment to Decrease Code Size. [Citation Graph (0, 0)][DBLP]
    PLDI, 1995, pp:186-195 [Conf]
  79. Matt Burnside, Dwaine E. Clarke, Todd Mills, Andrew Maywah, Srinivas Devadas, Ronald L. Rivest
    Proxy-based security protocols in networked mobile devices. [Citation Graph (0, 0)][DBLP]
    SAC, 2002, pp:265-272 [Conf]
  80. Blaise Gassend, Dwaine E. Clarke, Marten van Dijk, Srinivas Devadas
    Delay-Based Circuit Authentication and Applications. [Citation Graph (0, 0)][DBLP]
    SAC, 2003, pp:294-301 [Conf]
  81. Sanjay Raman, Dwaine E. Clarke, Matt Burnside, Srinivas Devadas, Ronald L. Rivest
    Access-Controlled Resource Discovery for Pervasive Networks. [Citation Graph (0, 0)][DBLP]
    SAC, 2003, pp:338-345 [Conf]
  82. Dwaine E. Clarke, G. Edward Suh, Blaise Gassend, Ajay Sudan, Marten van Dijk, Srinivas Devadas
    Towards Constant Bandwidth Overhead Integrity Checking of Untrusted Data. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Security and Privacy, 2005, pp:139-153 [Conf]
  83. Srinivas Devadas, Sharad Malik, José C. Monteiro, Luciano Lavagno
    CAD Techniques for Embedded System Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:608- [Conf]
  84. José C. Monteiro, James H. Kukula, Srinivas Devadas, Horácio C. Neto
    Bitwise Encoding of Finite State Machines. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:379-382 [Conf]
  85. Blaise Gassend, Charles W. O'Donnell, William Thies, Andrew Lee, Marten van Dijk, Srinivas Devadas
    Predicting Secondary Structure of All-Helical Proteins Using Hidden Markov Support Vector Machines. [Citation Graph (0, 0)][DBLP]
    PRIB, 2006, pp:93-104 [Conf]
  86. Blaise Gassend, Daihyun Lim, Dwaine E. Clarke, Marten van Dijk, Srinivas Devadas
    Identification and authentication of integrated circuits. [Citation Graph (0, 0)][DBLP]
    Concurrency - Practice and Experience, 2004, v:16, n:11, pp:1077-1098 [Journal]
  87. Sanjay Raman, Dwaine E. Clarke, Matt Burnside, Srinivas Devadas, Ronald L. Rivest
    Access-controlled resource discovery in pervasive networks. [Citation Graph (0, 0)][DBLP]
    Concurrency - Practice and Experience, 2004, v:16, n:11, pp:1099-1120 [Journal]
  88. Marten van Dijk, Dwaine E. Clarke, Blaise Gassend, G. Edward Suh, Srinivas Devadas
    Speeding up Exponentiation using an Untrusted Computational Resource. [Citation Graph (0, 0)][DBLP]
    Des. Codes Cryptography, 2006, v:39, n:2, pp:253-273 [Journal]
  89. Pranav Ashar, Srinivas Devadas, Kurt Keutzer
    Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1993, v:2, n:1, pp:93-112 [Journal]
  90. Filip Van Aelten, Jonathan Allen, Srinivas Devadas
    Verification of relations between synchronous machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:12, pp:1947-1959 [Journal]
  91. Filip Van Aelten, Jonathan Allen, Srinivas Devadas
    Event-based verification of synchronous, globally controlled, logic designs against signal flow graphs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:1, pp:122-134 [Journal]
  92. Pranav Ashar, Srinivas Devadas, A. Richard Newton
    Optimum and heuristic algorithms for an approach to finite state machine decomposition. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:3, pp:296-310 [Journal]
  93. Pranav Ashar, Srinivas Devadas, A. Richard Newton
    Irredundant interacting sequential machines via optimal logic synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:3, pp:311-325 [Journal]
  94. Douglas Braun, Jeffrey L. Burns, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli, Kartikeya Mayaram, Srinivas Devadas, Hi-Keung Tony Ma
    Techniques for multilayer channel routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:6, pp:698-712 [Journal]
  95. Michael J. Bryan, Srinivas Devadas, Kurt Keutzer
    Necessary and sufficient conditions for hazard-free robust transistor stuck-open-fault testability in multilevel networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:6, pp:800-803 [Journal]
  96. Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer
    Delay-fault test generation and synthesis for testability under a standard scan design methodology. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:8, pp:1217-1231 [Journal]
  97. Srinivas Devadas
    Optimizing interacting finite state machines using sequential don't cares. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:12, pp:1473-1484 [Journal]
  98. Srinivas Devadas
    Comparing two-level and ordered binary decision diagram representations of logic functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:5, pp:722-723 [Journal]
  99. Srinivas Devadas, Kurt Keutzer
    A unified approach to the synthesis of fully testable sequential machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:1, pp:39-50 [Journal]
  100. Srinivas Devadas, Kurt Keutzer
    Synthesis of robust delay-fault-testable circuits: theory. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:1, pp:87-101 [Journal]
  101. Srinivas Devadas, Kurt Keutzer
    Synthesis of robust delay-fault-testable circuits: practice. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:3, pp:277-300 [Journal]
  102. Srinivas Devadas, Kurt Keutzer
    Validatable nonrobust delay-fault testable circuits via logic synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:12, pp:1559-1573 [Journal]
  103. Srinivas Devadas, Kurt Keutzer
    Addendum to "Synthesis of robust delay-fault testable circuits: Theory". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:4, pp:445-446 [Journal]
  104. Srinivas Devadas, Kurt Keutzer, Sharad Malik
    Computation of floating mode delay in combinational circuits: theory and algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:12, pp:1913-1923 [Journal]
  105. Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang
    Computation of floating mode delay in combinational circuits: practice and implementation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:12, pp:1924-1936 [Journal]
  106. Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang
    Event suppression: improving the efficiency of timing simulation for synchronous digital circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:6, pp:814-822 [Journal]
  107. Srinivas Devadas, Kurt Keutzer, Jacob K. White
    Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:3, pp:373-383 [Journal]
  108. Srinivas Devadas, Hi-Keung Tony Ma
    Easily testable PLA-based finite state machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:6, pp:604-611 [Journal]
  109. Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton
    On the verification of sequential machines at differing levels of abstraction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:6, pp:713-722 [Journal]
  110. Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
    MUSTANG: state assignment of finite state machines targeting multilevel logic implementations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:12, pp:1290-1300 [Journal]
  111. Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
    A synthesis and optimization procedure for fully and easily testable sequential machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:10, pp:1100-1107 [Journal]
  112. Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
    Irredundant sequential machines via optimal logic synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:1, pp:8-18 [Journal]
  113. Srinivas Devadas, A. Richard Newton
    Topological Optimization of Multiple-Level Array Logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:6, pp:915-941 [Journal]
  114. Srinivas Devadas, A. Richard Newton
    Algorithms for hardware allocation in data path synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:7, pp:768-781 [Journal]
  115. Srinivas Devadas, A. Richard Newton
    Decomposition and factorization of sequential finite state machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:11, pp:1206-1217 [Journal]
  116. Srinivas Devadas, A. Richard Newton
    Exact algorithms for output encoding, state assignment, and four-level Boolean minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:1, pp:13-27 [Journal]
  117. Farzan Fallah, Srinivas Devadas, Kurt Keutzer
    Functional vector generation for HDL models using linearprogramming and Boolean satisfiability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:8, pp:994-1002 [Journal]
  118. Farzan Fallah, Srinivas Devadas, Kurt Keutzer
    OCCOM-efficient computation of observability-based code coveragemetrics for functional verification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:8, pp:1003-1015 [Journal]
  119. Abhijit Ghosh, Srinivas Devadas, A. Richard Newton
    Test generation and verification for highly sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:5, pp:652-667 [Journal]
  120. Abhijit Ghosh, Srinivas Devadas, A. Richard Newton
    Heuristic minimization of Boolean relations using testing techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:9, pp:1166-1172 [Journal]
  121. Abhijit Ghosh, Srinivas Devadas, A. Richard Newton
    Sequential test generation and synthesis for testability at the register-transfer and logic levels. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:5, pp:579-598 [Journal]
  122. Stan Y. Liao, Srinivas Devadas, Kurt Keutzer
    Code density optimization for embedded DSP processors using data compression techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:7, pp:601-608 [Journal]
  123. Bill Lin, Srinivas Devadas
    Synthesis of hazard-free multilevel logic under multiple-input changes from binary decision diagrams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:8, pp:974-985 [Journal]
  124. Hi-Keung Tony Ma, Srinivas Devadas, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
    Test generation for sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:10, pp:1081-1093 [Journal]
  125. Hi-Keung Tony Ma, Srinivas Devadas, Ruey-Sing Wei, Alberto L. Sangiovanni-Vincentelli
    Logic verification algorithms and their parallel implementation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:2, pp:181-189 [Journal]
  126. José C. Monteiro, Srinivas Devadas, Abhijit Ghosh
    Sequential logic optimization for low power using input-disabling precomputation architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:3, pp:279-284 [Journal]
  127. José C. Monteiro, Srinivas Devadas, Abhijit Ghosh, Kurt Keutzer, Jacob K. White
    Estimation of average switching activity in combinational logic circuits using symbolic simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:1, pp:121-127 [Journal]
  128. Amelia Shen, Srinivas Devadas, Abhijit Ghosh
    Probabilistic manipulation of Boolean functions using free Boolean diagrams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:1, pp:87-95 [Journal]
  129. Kenneth Y. Yun, Bill Lin, David L. Dill, Srinivas Devadas
    BDD-based synthesis of extended burst-mode controllers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:9, pp:782-792 [Journal]
  130. G. Edward Suh, Larry Rudolph, Srinivas Devadas
    Dynamic Partitioning of Shared Cache Memory. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2004, v:28, n:1, pp:7-26 [Journal]
  131. Stan Y. Liao, Srinivas Devadas, Kurt Keutzer
    A text-compression-based method for code size minimization in embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1999, v:4, n:1, pp:12-38 [Journal]
  132. Stan Y. Liao, Kurt Keutzer, Steven W. K. Tjiang, Srinivas Devadas
    A new viewpoint on code generation for directed acyclic graphs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:1, pp:51-75 [Journal]
  133. Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang, Albert Wang
    Storage Assignment to Decrease Code Size. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Program. Lang. Syst., 1996, v:18, n:3, pp:235-253 [Journal]
  134. Daihyun Lim, Jae W. Lee, Blaise Gassend, G. Edward Suh, Marten van Dijk, Srinivas Devadas
    Extracting secret keys from integrated circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:10, pp:1200-1205 [Journal]
  135. George Hadjiyiannis, Anantha Chandrakasan, Srinivas Devadas
    A low power, low bandwidth protocol for remote wireless terminals. [Citation Graph (0, 0)][DBLP]
    Wireless Networks, 1998, v:4, n:1, pp:3-15 [Journal]
  136. G. Edward Suh, Srinivas Devadas
    Physical Unclonable Functions for Device Authentication and Secret Key Generation. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:9-14 [Conf]
  137. Marten van Dijk, Emina Torlak, Blaise Gassend, Srinivas Devadas
    A Generalized Two-Phase Analysis of Knowledge Flows in Security Protocols [Citation Graph (0, 0)][DBLP]
    CoRR, 2006, v:0, n:, pp:- [Journal]
  138. Emina Torlak, Marten van Dijk, Blaise Gassend, Daniel Jackson, Srinivas Devadas
    Knowledge Flow Analysis for Security Protocols [Citation Graph (0, 0)][DBLP]
    CoRR, 2006, v:0, n:, pp:- [Journal]
  139. Horng-Fei Jyu, Sharad Malik, Srinivas Devadas, K. W. Keutzer
    Statistical timing analysis of combinational logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:2, pp:126-137 [Journal]
  140. Mazhar Alidina, J. Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou
    Precomputation-based sequential logic optimization for low power. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:4, pp:426-436 [Journal]
  141. Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang
    Certified timing verification and the transition delay of a logic circuit. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:3, pp:333-342 [Journal]
  142. Chi-Ying Tsui, José C. Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin
    Power estimation methods for sequential logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:3, pp:404-416 [Journal]
  143. Chi-Ying Tsui, José C. Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin
    Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:4, pp:495- [Journal]
  144. Farzan Fallah, Stan Y. Liao, Srinivas Devadas
    Solving covering problems using LPR-based lower bounds. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:1, pp:9-17 [Journal]
  145. Farzan Fallah, Pranav Ashar, Srinivas Devadas
    Functional vector generation for sequential HDL models under an observability-based code coverage metric. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:919-923 [Journal]
  146. George Hadjiyiannis, Srinivas Devadas
    Techniques for accurate performance evaluation in architecture exploration. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:4, pp:601-615 [Journal]

  147. Oblivious Routing in On-Chip Bandwidth-Adaptive Networks. [Citation Graph (, )][DBLP]


  148. The Trusted Execution Module: Commodity General-Purpose Trusted Computing. [Citation Graph (, )][DBLP]


  149. Offline untrusted storage with immediate detection of forking and replay attacks. [Citation Graph (, )][DBLP]


  150. Virtual monotonic counters and count-limited objects using a TPM without a trusted OS. [Citation Graph (, )][DBLP]


  151. Diastolic arrays: throughput-driven reconfigurable computing. [Citation Graph (, )][DBLP]


  152. Application-aware deadlock-free oblivious routing. [Citation Graph (, )][DBLP]


  153. Simultaneous Alignment and Folding of Protein Sequences. [Citation Graph (, )][DBLP]


  154. Offline count-limited certificates. [Citation Graph (, )][DBLP]


  155. Static virtual channel allocation in oblivious routing. [Citation Graph (, )][DBLP]


  156. Efficient stochastic simulation of reaction-diffusion processes via direct compilation. [Citation Graph (, )][DBLP]


  157. Learning biophysically-motivated parameters for alpha helix prediction. [Citation Graph (, )][DBLP]


  158. Aegis: A Single-Chip Secure Processor. [Citation Graph (, )][DBLP]


  159. Secure and Robust Error Correction for Physical Unclonable Functions. [Citation Graph (, )][DBLP]


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