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Chang Yun Park: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Do Han Kwon, Sung-Soo Kim, Chang Yun Park, Chung Il Jung
    Experiments on the Energy Saving and Performance Effects of IEEE 802.11 Power Saving Mode (PSM). [Citation Graph (0, 0)][DBLP]
    ICOIN, 2005, pp:41-51 [Conf]
  2. Yerang Hur, Young Hyun Bae, Sung-Soo Lim, Sung-Kwan Kim, Byung-Do Rhee, Sang Lyul Min, Chang Yun Park, Heonshik Shin, Chong-Sang Kim
    Worst Case Timing Analysis of RISC Processors: R3000/R3010 Case Study. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1995, pp:308-321 [Conf]
  3. Chang-Gun Lee, Joosun Hahn, Sang Lyul Min, Rhan Ha, Seongsoo Hong, Chang Yun Park, Minsuk Lee, Chong-Sang Kim
    Analysis of cache-related preemption delay in fixed-priority preemptive scheduling. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1996, pp:264-274 [Conf]
  4. Chang-Gun Lee, Joosun Hahn, Yang-Min Seo, Sang Lyul Min, Rhan Ha, Seongsoo Hong, Chang Yun Park, Minsuk Lee, Chong-Sang Kim
    Enhanced analysis of cache-related preemption delay in fixed-priority preemptive scheduling. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1997, pp:187-198 [Conf]
  5. Minsuk Lee, Sang Lyul Min, Chang Yun Park, Young Hyun Bae, Heonshik Shin, Chong-Sang Kim
    A Dual-Mode Instruction Prefetch Scheme for Improved Worst Case and Average Case Program Execution Times. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1993, pp:98-105 [Conf]
  6. Sung-Soo Lim, Young Hyun Bae, Gyu Tae Jang, Byung-Do Rhee, Sang Lyul Min, Chang Yun Park, Heonshik Shin, Kunsoo Park, Chong-Sang Kim
    An Accurate Worst Case Timing Analysis Technique for RISC Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1994, pp:142-151 [Conf]
  7. Chang Yun Park, Alan C. Shaw
    Experiments with a Program Timing Tool Based on Source-Level Timing Schema. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1990, pp:72-81 [Conf]
  8. Sheayun Lee, Jaejin Lee, Chang Yun Park, Sang Lyul Min
    A Flexible Tradeoff Between Code Size and WCET Using a Dual Instruction Set Processor. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2004, pp:244-258 [Conf]
  9. Sheayun Lee, Jaejin Lee, Chang Yun Park, Sang Lyul Min
    A Flexible Tradeoff between Code Size and WCET Employing Dual Instruction Set Processors. [Citation Graph (0, 0)][DBLP]
    WCET, 2003, pp:91-94 [Conf]
  10. Chang Yun Park, Alan C. Shaw
    Experiments with a Program Timing Tool Based on Source-Level Timing Schema. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1991, v:24, n:5, pp:48-57 [Journal]
  11. Minsuk Lee, Sang Lyul Min, Heonshik Shin, Chong-Sang Kim, Chang Yun Park
    Threaded Prefetching: A New Instruction Memory Hierarchy for Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    Real-Time Systems, 1997, v:13, n:1, pp:47-65 [Journal]
  12. Chang Yun Park
    Predicting Program Execution Times by Analyzing Static and Dynamic Program Paths. [Citation Graph (0, 0)][DBLP]
    Real-Time Systems, 1993, v:5, n:1, pp:31-62 [Journal]
  13. Chang-Gun Lee, Joosun Hahn, Yang-Min Seo, Sang Lyul Min, Rhan Ha, Seongsoo Hong, Chang Yun Park, Minsuk Lee, Chong-Sang Kim
    Analysis of Cache-Related Preemption Delay in Fixed-Priority Preemtive Scheduling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:6, pp:700-713 [Journal]
  14. Chang-Gun Lee, Kwangpo Lee, Joosun Hahn, Yang-Min Seo, Sang Lyul Min, Rhan Ha, Seongsoo Hong, Chang Yun Park, Minsuk Lee, Chong-Sang Kim
    Bounding Cache-Related Preemption Delay for Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Software Eng., 2001, v:27, n:9, pp:805-826 [Journal]
  15. Sung-Soo Lim, Young Hyun Bae, Gyu Tae Jang, Byung-Do Rhee, Sang Lyul Min, Chang Yun Park, Heonshik Shin, Kunsoo Park, Soo-Mook Moon, Chong-Sang Kim
    An Accurate Worst Case Timing Analysis for RISC Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Software Eng., 1995, v:21, n:7, pp:593-604 [Journal]
  16. Sheayun Lee, Jaejin Lee, Chang Yun Park, Sang Lyul Min
    Selective code transformation for dual instruction set processors. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2007, v:6, n:2, pp:- [Journal]

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