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Publications of Author

1. Ching-Long Su, Yin-Tsung Hwang
   Distributed arithmetic-based architectures for high speed IIR filter design. [Citation Graph (0, 0)][DBLP]
   ICPADS, 1996, pp:156-161 [Conf]
   
2. Yin-Tsung Hwang, Kuo-Wei Liao, Chien-Hsing Wu
   FPGA realization of an OFDM frame synchronization design for dispersive channels. [Citation Graph (0, 0)][DBLP]
   ISCAS (2), 2003, pp:256-259 [Conf]
   
3. Yin-Tsung Hwang, Chen-Yu Tsai, Cheng-Chen Lin
   Block-wise adaptive modulation for OFDM WLAN systems. [Citation Graph (0, 0)][DBLP]
   ISCAS (6), 2005, pp:6098-6101 [Conf]
   
4. Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang
   Systolic VLSI realization of a novel iterative division algorithm over GF(2m): a high-speed, low-complexity design. [Citation Graph (0, 0)][DBLP]
   ISCAS (4), 2001, pp:33-36 [Conf]
   
5. Yin-Tsung Hwang, Jih-Cheng Han, Jing-Yi Liu
   Design and implementation of channel equalizers for block transmission systems. [Citation Graph (0, 0)][DBLP]
   ISCAS (4), 2001, pp:354-357 [Conf]
   
6. Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Yin-Tsung Hwang, Jun-Hong Chen, Hsin-Fu Lo
   VLSI architecture exploration for sliding-window Log-MAP decoders. [Citation Graph (0, 0)][DBLP]
   ISCAS (2), 2004, pp:513-516 [Conf]
   
7. Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang
   An area-efficient systolic division circuit over GF(2/sup m/) for secure communication. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2002, pp:733-736 [Conf]
   
8. Yin-Tsung Hwang, Yuan-Hung Wang
   Communication and Interface Synthesis on a Rapid Prototyping Hardware/Software Codesign System. [Citation Graph (0, 0)][DBLP]
   ISSS, 1998, pp:76-82 [Conf]
   
9. Yin-Tsung Hwang, Jer-Sho Hwang
   Simulated Evolution Based Parallel Code Generation for Programmable DSP Processors. [Citation Graph (0, 0)][DBLP]
   J. Inf. Sci. Eng., 1998, v:14, n:1, pp:139-165 [Journal]
   
10. Yin-Tsung Hwang, Yuan-Hung Wang, Jer-Sho Hwang
    Rapid Prototyping of Hardware / Software Codesign for Embedded Signal Processing. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1998, v:14, n:3, pp:605-632 [Journal]
    
11. Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang
    High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m). [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:3, pp:375-380 [Journal]
    
12. Tai-Yi Huang, Chung-Ta King, Youn-Long Steve Lin, Yin-Tsung Hwang
    The embedded software consortium of taiwan. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2005, v:4, n:3, pp:612-632 [Journal]
    
13. Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Yin-Tsung Hwang, Jun-Hong Chen
    VLSI architectural design tradeoffs for sliding-window log-MAP decoders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:4, pp:439-447 [Journal]
    
14. Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu, Cheng-Che Ho
    A high speed and energy efficient full adder design using complementary & level restoring carry logic. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
    
15. 
    Space-Frequency-Coded MIMO OFDM Receivers Based on Gaussian Message Passing. [Citation Graph (, )][DBLP]
    
    
16. 
    A low complexity complex QR factorization design for signal detection in MIMO OFDM systems. [Citation Graph (, )][DBLP]
    
    
17. 
    Low Power Multiplier Designs Based on Improved Column Bypassing Schemes. [Citation Graph (, )][DBLP]
    
    
18. 
    A rapid prototyping embedded system platform and its HW/SW communication interface generation and verification. [Citation Graph (, )][DBLP]
    
    
19. 
    Automatic IP Interface Synthesis Supporting Multi-layer Communication Protocols in SoC Designs. [Citation Graph (, )][DBLP]
    
    
20. 
    Wavelet Based Lossless Video Compression Using Motion Compensated Temporal Filtering. [Citation Graph (, )][DBLP]
    
    
21. 
    Low Power Multipliers Using Enhenced Row Bypassing Schemes. [Citation Graph (, )][DBLP]
    
    
22. 
    Automatic Generation of Programmable Parallel CRC & Scrambler Designs. [Citation Graph (, )][DBLP]