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Publications of Author

1. Akira Yamawaki, Masahiko Iwane
   Organization of Shared Memory with Synchronization for Multiprocessor-on-a-chip. [Citation Graph (0, 0)][DBLP]
   ICPADS, 2002, pp:83-90 [Conf]
   
2. Akira Yamawaki, Masahiko Iwane
   Evaluation of mechanisms introduced to improve performance of TSVM cache. [Citation Graph (0, 0)][DBLP]
   Parallel and Distributed Computing and Networks, 2004, pp:502-507 [Conf]
   
3. Akira Yamawaki, Masahiko Iwane
   An efficient parallel processing using a cache memory with synchronization on a Soc-multiprocessor. [Citation Graph (0, 0)][DBLP]
   Circuits, Signals, and Systems, 2005, pp:142-147 [Conf]
   
4. Masahiko Iwane, Akira Yamawaki, Makoto Tanaka
   Tagged communication and synchronization memory for multiprocessor-on-a-chip. [Citation Graph (0, 0)][DBLP]
   Systems and Computers in Japan, 2001, v:32, n:4, pp:1-13 [Journal]
   
5. 
   An Efficient Comparative Evaluation to Buffering Methods for Window-based Image Processing Using Semi-programmable Hardware. [Citation Graph (, )][DBLP]
   
   
6. 
   An intermediate hardware model with load/store unit for C to FPGA. [Citation Graph (, )][DBLP]
   
   
7. 
   An Efficient Hardware Architecture from C Program with Memory Access to Hardware. [Citation Graph (, )][DBLP]
   
   
8. 
   An FPGA implementation of a snoop cache with synchronization for a multiprocessor system-on-chip. [Citation Graph (, )][DBLP]
   
   
9. 
   Coherence Maintenances to realize an efficient parallel processing for a Cache Memory with Synchronization on a Chip-Multiprocessor. [Citation Graph (, )][DBLP]