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Marc González: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Eduard Ayguadé, Xavier Martorell, Jesús Labarta, Marc González, Nacho Navarro
    Exploiting Multiple Levels of Parallelism in OpenMP: A Case Study. [Citation Graph (0, 0)][DBLP]
    ICPP, 1999, pp:172-180 [Conf]
  2. Marc González, Eduard Ayguadé, Xavier Martorell, Jesús Labarta
    Complex Pipelined Executions in OpenMP Parallel Applications. [Citation Graph (0, 0)][DBLP]
    ICPP, 2001, pp:295-304 [Conf]
  3. Alejandro Duran, Marc González, Julita Corbalán
    Automatic thread distribution for nested parallelism in OpenMP. [Citation Graph (0, 0)][DBLP]
    ICS, 2005, pp:121-130 [Conf]
  4. Xavier Martorell, Eduard Ayguadé, Nacho Navarro, Julita Corbalán, Marc González, Jesús Labarta
    Thread fork/join techniques for multi-level parallelism exploitation in NUMA multiprocessors. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1999, pp:294-301 [Conf]
  5. Eduard Ayguadé, Marc González, Xavier Martorell, Gabriele Jost
    Employing Nested OpenMP for the Parallelization of Multi-Zone Computational Fluid Dynamics Applications. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  6. Marc González, Albert Serra, Xavier Martorell, José Oliver, Eduard Ayguadé, Jesús Labarta, Nacho Navarro
    Applying Interposition Techniques for Performance Analysis of OpenMP Parallel Applications. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2000, pp:235-240 [Conf]
  7. Xavier Martorell, Marc González, Alejandro Duran, Jairo Balart, Roger Ferrer, Eduard Ayguadé, Jesús Labarta
    Techniques supporting threadprivate in OpenMP. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  8. Marc González, Eduard Ayguadé, Xavier Martorell, Jesús Labarta, Phu V. Luong
    Dual-Level Parallelism Exploitation with OpenMP in Coastal Ocean Circulation Modeling. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2002, pp:469-478 [Conf]
  9. Eduard Ayguadé, Xavier Martorell, Jesús Labarta, Marc González, Nacho Navarro
    Exploiting Parallelism Through Directives on the Nano-Threads Programming Model. [Citation Graph (0, 0)][DBLP]
    LCPC, 1997, pp:307-321 [Conf]
  10. Marc González, José Oliver, Xavier Martorell, Eduard Ayguadé, Jesús Labarta, Nacho Navarro
    OpenMP Extensions for Thread Groups and Their Run-Time Support. [Citation Graph (0, 0)][DBLP]
    LCPC, 2000, pp:324-338 [Conf]
  11. Marc González, Eduard Ayguadé, Xavier Martorell, Jesús Labarta
    Defining and Supporting Pipelined Executions in OpenMP. [Citation Graph (0, 0)][DBLP]
    WOMPAT, 2001, pp:155-169 [Conf]
  12. Marc González, Eduard Ayguadé, Xavier Martorell, Jesús Labarta, Nacho Navarro, José Oliver
    NanosCompiler: supporting flexible multilevel parallelism exploitation in OpenMP. [Citation Graph (0, 0)][DBLP]
    Concurrency - Practice and Experience, 2000, v:12, n:12, pp:1205-1218 [Journal]
  13. Eduard Ayguadé, Marc González, Xavier Martorell, Gabriele Jost
    Employing nested OpenMP for the parallelization of multi-zone computational fluid dynamics applications. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2006, v:66, n:5, pp:686-697 [Journal]
  14. Haoqiang Jin, Gabriele Jost, Jerry Yan, Eduard Ayguadé, Marc González, Xavier Martorell
    Automatic multilevel parallelization using OpenMP. [Citation Graph (0, 0)][DBLP]
    Scientific Programming, 2003, v:11, n:2, pp:177-190 [Journal]
  15. Jairo Balart, Marc González, Xavier Martorell, Eduard Ayguadé, Jesús Labarta
    Runtime Address Space Computation for SDSM Systems. [Citation Graph (0, 0)][DBLP]
    LCPC, 2006, pp:330-344 [Conf]
  16. Alejandro Duran, Roger Ferrer, Juan José Costa, Marc González, Xavier Martorell, Eduard Ayguadé, Jesús Labarta
    A Proposal for Error Handling in OpenMP. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2007, v:35, n:4, pp:393-416 [Journal]

  17. Hybrid access-specific software cache techniques for the cell BE architecture. [Citation Graph (, )][DBLP]


  18. Analysis of Task Offloading for Accelerators. [Citation Graph (, )][DBLP]


  19. Speeding Up Distributed MapReduce Applications Using Hardware Accelerators. [Citation Graph (, )][DBLP]


  20. Decomposable and responsive power models for multicore processors using performance counters. [Citation Graph (, )][DBLP]


  21. A Novel Asynchronous Software Cache Implementation for the Cell-BE Processor. [Citation Graph (, )][DBLP]


  22. Automatic Pre-Fetch and Modulo Scheduling Transformations for the Cell BE Architecture. [Citation Graph (, )][DBLP]


  23. A Proposal to Extend the OpenMP Tasking Model for Heterogeneous Architectures. [Citation Graph (, )][DBLP]


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