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Utpal Banerjee: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Pohua P. Chang, Utpal Banerjee
    Profile-Guided Multi-Heuristic Branch Prediction. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1995, pp:215-218 [Conf]
  2. Constantine D. Polychronopoulos, Utpal Banerjee
    Speedup Bounds and Processor Allocation for Parallel Programs on Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICPP, 1986, pp:961-968 [Conf]
  3. Arun Kejariwal, Xinmin Tian, Wei Li, Milind Girkar, Sergey Kozhukhov, Hideki Saito, Utpal Banerjee, Alexandru Nicolau, Alexander V. Veidenbaum, Constantine D. Polychronopoulos
    On the performance potential of different types of speculative thread-level parallelism: The DL version of this paper includes corrections that were not made available in the printed proceedings. [Citation Graph (0, 0)][DBLP]
    ICS, 2006, pp:24- [Conf]
  4. Arun Kejariwal, Hideki Saito, Xinmin Tian, Milind Girkar, Wei Li, Utpal Banerjee, Alexandru Nicolau, Constantine D. Polychronopoulos
    Lightweight lock-free synchronization methods for multithreading. [Citation Graph (0, 0)][DBLP]
    ICS, 2006, pp:361-371 [Conf]
  5. Utpal Banerjee, Daniel Gajski
    Fast Execution of Loops With IF Statements. [Citation Graph (0, 0)][DBLP]
    ISCA, 1984, pp:126-132 [Conf]
  6. Pohua P. Chang, Dong-yuan Chen, Yong-Fong Lee, Youfeng Wu, Utpal Banerjee
    Bidirectional Scheduling: A New Global Code Scheduling Approach. [Citation Graph (0, 0)][DBLP]
    LCPC, 1996, pp:222-230 [Conf]
  7. K. Sridharan, Pohua P. Chang, Utpal Banerjee, Ravi Narayanaswamy, Suresh Rao
    Memory Optimizations in the Intel Reference Compiler. [Citation Graph (0, 0)][DBLP]
    LCPC, 1996, pp:608-610 [Conf]
  8. James Radigan, Pohua P. Chang, Utpal Banerjee
    Integer Loop Code Generation for VLIW. [Citation Graph (0, 0)][DBLP]
    LCPC, 1995, pp:318-330 [Conf]
  9. Arun Kejariwal, Alexandru Nicolau, Utpal Banerjee, Constantine D. Polychronopoulos
    A novel approach for partitioning iteration spaces with variable densities. [Citation Graph (0, 0)][DBLP]
    PPOPP, 2005, pp:120-131 [Conf]
  10. Arun Kejariwal, Xinmin Tian, Milind Girkar, Wei Li, Sergey Kozhukhov, Utpal Banerjee, Alexandru Nicolau, Alexander V. Veidenbaum, Constantine D. Polychronopoulos
    Tight analysis of the performance potential of thread speculation using spec CPU 2006. [Citation Graph (0, 0)][DBLP]
    PPOPP, 2007, pp:215-225 [Conf]
  11. Arun Kejariwal, Alexandru Nicolau, Hideki Saito, Xinmin Tian, Milind Girkar, Utpal Banerjee, Constantine D. Polychronopoulos
    A general approach for partitioning N-dimensional parallel nested loops with conditionals. [Citation Graph (0, 0)][DBLP]
    SPAA, 2006, pp:49-58 [Conf]
  12. Utpal Banerjee
    Guest Editor's Introduction. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2004, v:32, n:3, pp:165-166 [Journal]
  13. Utpal Banerjee
    Guest Editor's Introduction. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2004, v:32, n:4, pp:259-261 [Journal]
  14. Utpal Banerjee, Shyh-Ching Chen, David J. Kuck, Ross A. Towle
    Time and Parallel Processor Bounds for Fortran-Like Loops. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1979, v:28, n:9, pp:660-670 [Journal]
  15. Utpal Banerjee, Daniel Gajski
    Fast Execution of Loops with IF Statements. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1984, v:33, n:11, pp:1030-1033 [Journal]
  16. Constantine D. Polychronopoulos, Utpal Banerjee
    Processor Allocation for Horizontal and Vertical Parallelism and Related Speedup Bounds. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1987, v:36, n:4, pp:410-420 [Journal]
  17. Youfeng Wu, Utpal Banerjee, Yong-Fong Lee
    Calculation of Load Invalidation Rates for Data Speculation. [Citation Graph (0, 0)][DBLP]
    ISCA PDCS, 2001, pp:75-82 [Conf]

  18. Exploitation of nested thread-level speculative parallelism on multi-core systems. [Citation Graph (, )][DBLP]


  19. Efficient Scheduling of Nested Parallel Loops on Multi-Core Systems. [Citation Graph (, )][DBLP]


  20. A theory of data race detection. [Citation Graph (, )][DBLP]


  21. Cache-aware iteration space partitioning. [Citation Graph (, )][DBLP]


  22. Comparative architectural characterization of SPEC CPU2000 and CPU2006 benchmarks on the intel® CoreTM 2 Duo processor. [Citation Graph (, )][DBLP]


  23. On the efficacy of call graph-level thread-level speculation. [Citation Graph (, )][DBLP]


  24. Cache-aware partitioning of multi-dimensional iteration spaces. [Citation Graph (, )][DBLP]


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