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David T. Harper III: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. David T. Harper III
    Address Transformations to Increase Memory Performance. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1989, pp:237-241 [Conf]
  2. David T. Harper III, Darel A. Linebarger
    Storage Schemes for Efficient Computation of a Radix 2 FFT in a Machine with Parallel Memories. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1988, pp:422-425 [Conf]
  3. David T. Harper III
    Reducing Memory Contention in Shared Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1991, pp:66-73 [Conf]
  4. David T. Harper III, J. Robert Jump
    Performance Evaluation of Vector Accesses in Parallel Memories Using a Skewed Storage Scheme. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:324-328 [Conf]
  5. David T. Harper III, J. Robert Jump
    Performance Evaluation of Reduced Bandwidth Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    ISCA, 1987, pp:171-175 [Conf]
  6. David T. Harper III, Darel A. Linebarger
    A Dynamic Storage Scheme for Conflict-Free Vector Access. [Citation Graph (0, 0)][DBLP]
    ISCA, 1989, pp:72-77 [Conf]
  7. David T. Harper III, David Tuma
    A Parallel Algorithm for Cache Miss Ratio Evaluation. [Citation Graph (0, 0)][DBLP]
    MASCOTS, 1993, pp:79-82 [Conf]
  8. Jong Won Park, David T. Harper III
    Memory Architecture Support for the SIMD Construction of a Gaussian Pyramid. [Citation Graph (0, 0)][DBLP]
    SPDP, 1992, pp:444-451 [Conf]
  9. David T. Harper III, J. Robert Jump
    Evaluation of Reduced Bandwidth Multistage Networks. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1990, v:9, n:3, pp:304-311 [Journal]
  10. David T. Harper III
    Increased Memory Performance During Vector Accesses Through the use of Linear Address Transformations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:2, pp:227-230 [Journal]
  11. David T. Harper III
    A Multiaccess Frame Buffer Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:5, pp:618-622 [Journal]
  12. David T. Harper III, Yashodara Costa
    Analytical Estimation of Vector Access Performance in Parallel Memory Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:5, pp:616-624 [Journal]
  13. David T. Harper III, J. Robert Jump
    Vector Access Performance in Parallel Memories Using a Skewed Storage Scheme. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1987, v:36, n:12, pp:1440-1449 [Journal]
  14. David T. Harper III, Darel A. Linebarger
    Conflict-Free Vector Access Using a Dynamic Storage Scheme. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:3, pp:276-283 [Journal]
  15. David T. Harper III
    Block, Multistride Vector, and FFT Accesses in Parallel Memory Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1991, v:2, n:1, pp:43-51 [Journal]
  16. Jong Won Park, David T. Harper III
    An Efficient Memory System for the SIMD Construction of a Gaussian Pyramid. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1996, v:7, n:8, pp:855-860 [Journal]

  17. An interleaved array-processing architecture. [Citation Graph (, )][DBLP]


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