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Manish Sharma: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jeff Konicek, Tracy Tilton, Alexander V. Veidenbaum, Chuan-Qi Zhu, Edward S. Davidson, Ruppert A. Downing, Michael J. Haney, Manish Sharma, Pen-Chung Yew, P. Michael Farmwald, David J. Kuck, Daniel M. Lavery, Robert A. Lindsey, D. Pointer, John T. Andrews, Thomas Beck, T. Murphy, Stephen W. Turner, Nancy J. Warter
    The Organization of the Cedar System. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1991, pp:49-56 [Conf]
  2. Manish Sharma, Janak H. Patel
    Enhanced delay defect coverage with path-segments. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:385-392 [Conf]
  3. Manish Sharma, Janak H. Patel
    Testing of critical paths for delay faults. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:634-641 [Conf]
  4. Manish Sharma, Janak H. Patel
    Finding a Small Set of Longest Testable Paths that Cover Every Gate. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:974-982 [Conf]
  5. C. P. Ravikumar, Manish Sharma, R. K. Patney
    Improving the Diagnosability of Digital Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:629-634 [Conf]
  6. Keerthi Heragu, Manish Sharma, Rahul Kundu, R. D. (Shawn) Blanton
    Testing of Dynamic Logic Circuits Based on Charge Sharing. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:396-403 [Conf]
  7. Manish Sharma, Janak H. Patel
    Bounding Circuit Delay by Testing a Very Small Subset of Paths. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:333-342 [Conf]
  8. Manish Sharma, Janak H. Patel
    What Does Robust Testing a Subset of Paths, Tell us about the Untested Paths in the Circuit? [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:31-36 [Conf]
  9. Manish Sharma, Janak H. Patel, Jeff Rearick
    Test Data Compression and Test Time Reduction of Longest-Path-Per-Gate Tests based on Illinois Scan Architecture. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:15-21 [Conf]
  10. Keerthi Heragu, Manish Sharma, Rahul Kundu, Ronald D. Blanton
    Test vector generation for charge sharing failures in dynamic logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:12, pp:1502-1508 [Journal]
  11. Huaxing Tang, Sharma Manish, Janusz Rajski, Martin Keim, Brady Benware
    Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:145-150 [Conf]

  12. A Simulation-based strategy used in electrical design for reliability. [Citation Graph (, )][DBLP]


  13. Wavelet Based Adaptive Tracking Control for Uncertain Nonlinear Systems with Input Constraints. [Citation Graph (, )][DBLP]


  14. Wavelet Adaptive Observer Based Control for a Class of Uncertain Time Delay Nonlinear Systems with Input Constraints. [Citation Graph (, )][DBLP]


  15. X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis. [Citation Graph (, )][DBLP]


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