The SCEAS System
Navigation Menu
Introduction
Collection Based
Clustering
Ranking
Paper Based
Journals
Conferences
DB Status
Statistics
Search

Search the dblp DataBase

Title:
Author:
Yu-Chen Tsai: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Viktor K. Prasanna, Yu-Chen Tsai
    Mapping Two Dimensional Systolic Arrays to One Dimensional Arrays and Applications. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1988, pp:39-46 [Conf]
  2. Viktor K. Prasanna, Yu-Chen Tsai
    Designing Linear Systolic Arrays. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1989, v:7, n:3, pp:441-463 [Journal]
  3. Viktor K. Prasanna, Yu-Chen Tsai
    On Mapping Algorithms to Linear and Fault-Tolerant Systolic Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1989, v:38, n:3, pp:470-478 [Journal]
  4. Viktor K. Prasanna, Yu-Chen Tsai
    On Synthesizing Optimal Family of Linear Systolic Arrays for Matrix Multiplication. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:6, pp:770-774 [Journal]
  5. Shyue-Kung Lu, Yu-Chen Tsai, Chih-Hsien Hsu, Kuo-Hua Wang, Cheng-Wen Wu
    Efficient built-in redundancy analysis for embedded memories with 2-D redundancy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:1, pp:34-42 [Journal]

Search in 0.001secs, Finished in 0.001secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
Introduction Collection Based Clustering Ranking Paper Based Journals Conferences DB Status Statistics Search
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002