T. K. Priya, K. Sridharan An Efficient Algorithm to Construct Reduced Visibility Graph and Its FPGA Implementation. [Citation Graph (0, 0)][DBLP] VLSI Design, 2004, pp:1057-1062 [Conf]
K. Sridharan Efficient computation of a measure of depth between convex objects for graphics applications. [Citation Graph (0, 0)][DBLP] Computers & Graphics, 2002, v:26, n:5, pp:785-793 [Journal]
K. Sridharan Computing two penetration measures for curved 2D objects. [Citation Graph (0, 0)][DBLP] Inf. Process. Lett., 1999, v:72, n:3-4, pp:143-148 [Journal]
K. Sridharan, T. K. Priya A parallel algorithm for constructing reduced visibility graph and its FPGA implementation. [Citation Graph (0, 0)][DBLP] Journal of Systems Architecture, 2004, v:50, n:10, pp:635-644 [Journal]
P. Rajesh Kumar, K. Sridharan, S. Srinivasan A parallel algorithm, architecture and FPGA realization for landmark determination and map construction in a planar unknown environment. [Citation Graph (0, 0)][DBLP] Parallel Computing, 2006, v:32, n:3, pp:205-221 [Journal]
T. K. Priya, P. Rajesh Kumar, K. Sridharan A hardware-efficient scheme and FPGA realization for computation of single pair shortest path for a mobile automaton. [Citation Graph (0, 0)][DBLP] Microprocessors and Microsystems, 2006, v:30, n:7, pp:413-424 [Journal]
T. K. Priya, K. Sridharan A parallel algorithm, architecture and FPGA realization for high speed determination of the complete visibility graph for convex objects. [Citation Graph (0, 0)][DBLP] Microprocessors and Microsystems, 2006, v:30, n:1, pp:1-14 [Journal]
P. Rajesh Kumar, K. Sridharan VLSI-Efficient Scheme and FPGA Realization for Robotic Mapping in a Dynamic Environment. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2007, v:15, n:1, pp:118-123 [Journal]
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