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Publications of Author

1. Y. Kuroda, J. Miyakoshi, M. Miyama, Kousuke Imamura, Hideo Hashimoto, M. Yoshimoto
   A sub-mW MPEG-4 motion estimation processor core for mobile video application. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2004, pp:527-528 [Conf]
   
2. A. Watanabe, O. Tooyama, M. Miyama, M. Yoshimoto, J. Akita
   An image sensor with fast extraction of objects' positions - rough vision processor. [Citation Graph (0, 0)][DBLP]
   ICIP (2), 2001, pp:1105-1108 [Conf]
   
3. Takafumi Aonishi, Takashi Matsuda, Shinji Mikami, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto
   Impact of Aggregation Efficiency on GIT Routing forWireless Sensor Networks. [Citation Graph (0, 0)][DBLP]
   ICPP Workshops, 2006, pp:151-158 [Conf]
   
4. Hidehiro Fujiwara, Koji Nii, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto
   A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2006, pp:61-66 [Conf]
   
5. Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
   A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing. [Citation Graph (0, 0)][DBLP]
   ISVLSI, 2007, pp:107-112 [Conf]
   
6. Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi, Masahiko Yoshimoto, Tetsuro Matsuno
   A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing. [Citation Graph (0, 0)][DBLP]
   VLSI-SoC, 2006, pp:192-197 [Conf]
   
7. 
   Power and Memory Bandwidth Reduction of an H.264/AVC HDTV Decoder LSI with Elastic Pipeline Architecture. [Citation Graph (, )][DBLP]
   
   
8. 
   A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding. [Citation Graph (, )][DBLP]
   
   
9. 
   0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM. [Citation Graph (, )][DBLP]
   
   
10. 
    Quality of a Bit (QoB): A New Concept in Dependable SRAM. [Citation Graph (, )][DBLP]
    
    
11. 
    A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme. [Citation Graph (, )][DBLP]
    
    
12. 
    A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection. [Citation Graph (, )][DBLP]
    
    
13. 
    An ultra-low-power VAD hardware implementation for intelligent ubiquitous sensor networks. [Citation Graph (, )][DBLP]