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Michael Kishinevsky: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Alex Kondratyev, Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexander Taubin, Alexandre Yakovlev
    Identifying State Coding Conflicts in Asynchronous System Specifications Using Petri Net Unfoldings. [Citation Graph (0, 0)][DBLP]
    ACSD, 1998, pp:152-0 [Conf]
  2. Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexandre Yakovlev
    Hardware and Petri Nets: Application to Asynchronous Circuit Design. [Citation Graph (0, 0)][DBLP]
    ICATPN, 2000, pp:1-15 [Conf]
  3. Michael Kishinevsky, Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Alexander Taubin, Alexandre Yakovlev
    Coupling Asynchrony and Interrupts: Place Chart Nets. [Citation Graph (0, 0)][DBLP]
    ICATPN, 1997, pp:328-347 [Conf]
  4. Alex Kondratyev, Michael Kishinevsky, Alexander Taubin, Sergei Ten
    A Structural Approach for the Analysis of Petri Nets by Reduced Unfoldings. [Citation Graph (0, 0)][DBLP]
    Application and Theory of Petri Nets, 1996, pp:346-365 [Conf]
  5. Alexandre Yakovlev, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno
    OR Causality: Modelling and Hardware Implementation. [Citation Graph (0, 0)][DBLP]
    Application and Theory of Petri Nets, 1994, pp:568-587 [Conf]
  6. Alex Kondratyev, Michael Kishinevsky, Alexandre Yakovlev
    On hazard-free implementation of speed-independent circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  7. Alex Kondratyev, Michael Kishinevsky, Jordi Cortadella, Luciano Lavagno, Alexandre Yakovlev
    Technology Mapping for Speed-Independent Circuits: Decomposition and Resynthesis. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1997, pp:240-253 [Conf]
  8. Michael Kishinevsky, Jordi Cortadella, Bill Grundmann, Sava Krstic, John O'Leary
    Synchronous Elastic Circuits. [Citation Graph (0, 0)][DBLP]
    CSR, 2006, pp:3-5 [Conf]
  9. David Bañeres, Jordi Cortadella, Michael Kishinevsky
    A recursive paradigm to solve Boolean relations. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:416-421 [Conf]
  10. Jordi Cortadella, Michael Kishinevsky, Bill Grundmann
    Synthesis of synchronous elastic architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:657-662 [Conf]
  11. Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexandre Yakovlev
    Methodology and Tools for State Encoding in Asynchronous Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:63-66 [Conf]
  12. Sumit Gupta, Nick Savoiu, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau, Timothy Kam, Michael Kishinevsky, Shai Rotem
    Coordinated transformations for high-level synthesis of high performance microprocessor blocks. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:898-903 [Conf]
  13. Michael Kishinevsky, Jordi Cortadella, Alex Kondratyev
    Asynchronous Interface Specification, Analysis and Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:2-7 [Conf]
  14. Alex Kondratyev, Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexandre Yakovlev
    Automatic Synthesis and Optimization of Partially Specified Asynchronous Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:110-115 [Conf]
  15. Alex Kondratyev, Michael Kishinevsky, Bill Lin, Peter Vanbekbergen, Alexandre Yakovlev
    Basic Gate Implementation of Speed-Independent Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:56-62 [Conf]
  16. Christian D. Nielsen, Michael Kishinevsky
    Performance Analysis Based on Timing Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:70-76 [Conf]
  17. Ken S. Stevens, Shai Rotem, Steven M. Burns, Jordi Cortadella, Ran Ginosar, Michael Kishinevsky, Marly Roncken
    CAD Directions for High Performance Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:116-121 [Conf]
  18. Laurent Arditi, Gérard Berry, Michael Kishinevsky
    Late Design Changes (ECOs) for Sequentially Optimized Esterel Designs. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2004, pp:128-143 [Conf]
  19. Sava Krstic, Jordi Cortadella, Michael Kishinevsky, John O'Leary
    Synchronous Elastic Networks. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2006, pp:19-30 [Conf]
  20. David Bañeres, Jordi Cortadella, Michael Kishinevsky
    Dominator-based partitioning for delay optimization. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:67-72 [Conf]
  21. Gérard Berry, Michael Kishinevsky, Satnam Singh
    System Level Design and Verification Using a Synchronous Language. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:433-440 [Conf]
  22. Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Ken S. Stevens
    Synthesis of asynchronous control circuits with automatically generated relative timing assumptions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:324-331 [Conf]
  23. Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Enric Pastor, Alexandre Yakovlev
    Decomposition and technology mapping of speed-independent circuits using Boolean relations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:220-227 [Conf]
  24. Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Taubin, Alexandre Yakovlev
    Lazy transition systems: application to timing optimization of asynchronous circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:324-331 [Conf]
  25. Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexandre Yakovlev
    Synthesizing Petri nets from state-based models. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:164-171 [Conf]
  26. Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Saldanha, Alexander Taubin
    Partial scan delay fault testing of asynchronous circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:728-735 [Conf]
  27. Jorge Júlvez, Jordi Cortadella, Michael Kishinevsky
    Performance analysis of concurrent systems with early evaluation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:448-455 [Conf]
  28. Michael Kishinevsky, Alex Kondratyev, Alexander Taubin, Victor Varshavsky
    Analysis and Identification of Self-Timed Circuits. [Citation Graph (0, 0)][DBLP]
    Designing Correct Circuits, 1992, pp:275-287 [Conf]
  29. Michael Kishinevsky, Alex Kondratyev, Alexander Taubin, Victor Varshavsky
    Analysis and Identification of Speed-Independent Circuits on an Event Model. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1994, v:4, n:1, pp:33-75 [Journal]
  30. Alex Kondratyev, Michael Kishinevsky, Alexander Taubin, Sergei Ten
    Analysis of Petri Nets by Ordering Relations in Reduced Unfoldings. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1998, v:12, n:1, pp:5-38 [Journal]
  31. Alexandre Yakovlev, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Marta Pietkiewicz-Koutny
    On the Models for Asynchronous Circuit Behaviour with OR Causality. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1996, v:9, n:3, pp:189-233 [Journal]
  32. Alex Kondratyev, Michael Kishinevsky, Alexander Taubin, Jordi Cortadella, Luciano Lavagno
    The Use of Petri Nets for the Design and Verification of Asynchronous Circuits and Systems. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 1998, v:8, n:1, pp:67-118 [Journal]
  33. Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexandre Yakovlev
    Deriving Petri Nets for Finite Transition Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:8, pp:859-882 [Journal]
  34. Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Alex Kondratyev, Luciano Lavagno, Ken S. Stevens, Alexander Taubin, Alexandre Yakovlev
    Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:2, pp:109-130 [Journal]
  35. Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Enric Pastor, Alexandre Yakovlev
    Decomposition and technology mapping of speed-independent circuits using Boolean relations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1221-1236 [Journal]
  36. Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexandre Yakovlev
    A region-based theory for state assignment in speed-independent circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:8, pp:793-812 [Journal]
  37. Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Saldanha, Alexander Taubin
    Partial-scan delay fault testing of asynchronous circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:11, pp:1184-1199 [Journal]
  38. Alex Kondratyev, Michael Kishinevsky, Alexandre Yakovlev
    Hazard-free implementation of speed-independent circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:9, pp:749-771 [Journal]
  39. Jordi Cortadella, Michael Kishinevsky
    Synchronous Elastic Circuits with Early Evaluation and Token Counterflow. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:416-419 [Conf]
  40. David Bañeres, Jordi Cortadella, Michael Kishinevsky
    Layout-aware gate duplication and buffer insertion. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1367-1372 [Conf]

  41. Scheduling Synchronous Elastic Designs. [Citation Graph (, )][DBLP]


  42. Time elastic digital systems and Petri Nets. [Citation Graph (, )][DBLP]


  43. Genet: A Tool for the Synthesis and Mining of Petri Nets. [Citation Graph (, )][DBLP]


  44. A Symbolic Algorithm for the Synthesis of Bounded Petri Nets. [Citation Graph (, )][DBLP]


  45. A Region-Based Algorithm for Discovering Petri Nets from Event Logs. [Citation Graph (, )][DBLP]


  46. Divide-and-Conquer Strategies for Process Mining. [Citation Graph (, )][DBLP]


  47. Automatic Generation of Inductive Invariants from High-Level Microarchitectural Models of Communication Fabrics. [Citation Graph (, )][DBLP]


  48. Speculation in elastic systems. [Citation Graph (, )][DBLP]


  49. Retiming and recycling for elastic systems with early evaluation. [Citation Graph (, )][DBLP]


  50. Technology mapping of speed-independent circuits based on combinational decomposition and resynthesis. [Citation Graph (, )][DBLP]


  51. Variable-latency design by function speculation. [Citation Graph (, )][DBLP]


  52. Automatic microarchitectural pipelining. [Citation Graph (, )][DBLP]


  53. Testing redundant asynchronous circuits by variable phase splitting. [Citation Graph (, )][DBLP]


  54. Timing-driven N-way decomposition. [Citation Graph (, )][DBLP]


  55. A general model for performance optimization of sequential systems. [Citation Graph (, )][DBLP]


  56. Correct-by-construction microarchitectural pipelining. [Citation Graph (, )][DBLP]


  57. A System Verilog Rewriting System for RTL Abstraction with Pentium Case Study. [Citation Graph (, )][DBLP]


  58. Physical-Aware Link Allocation and Route Assignment for Chip Multiprocessing. [Citation Graph (, )][DBLP]


  59. Guest Editors' Introduction: GALS Design and Validation. [Citation Graph (, )][DBLP]


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