The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Carl Pixley: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jainendra Kumar, Carl Pixley
    Logic and Functional Verification in a Commercial Semiconductor Environment. [Citation Graph (0, 0)][DBLP]
    ACSD, 1998, pp:8-15 [Conf]
  2. Matt Kaufmann, Andrew Martin, Carl Pixley
    Design Constraints in Symbolic Model Checking. [Citation Graph (0, 0)][DBLP]
    CAV, 1998, pp:477-487 [Conf]
  3. Carl Pixley
    Introduction to a Computational Theory and Implementation of Sequential Hardware Equivalence. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:54-64 [Conf]
  4. Vigyan Singhal, Carl Pixley
    The Verifiacation Problem for Safe Replaceability. [Citation Graph (0, 0)][DBLP]
    CAV, 1994, pp:311-323 [Conf]
  5. Rajesh K. Gupta, Shishpal Rawat, Sandeep K. Shukla, Brian Bailey, Daniel K. Beece, Masahiro Fujita, Carl Pixley, John O'Leary, Fabio Somenzi
    Formal verification - prove it or pitch it. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:710-711 [Conf]
  6. Jae-Young Jang, Shaz Qadeer, Matt Kaufmann, Carl Pixley
    Formal Verification of FIRE: A Case Study. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:173-177 [Conf]
  7. Carl Pixley, Seh-Woong Jeong, Gary D. Hachtel
    Exact Calculation of Synchronization Sequences Based on Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:620-623 [Conf]
  8. June-Kyung Rho, Fabio Somenzi, Carl Pixley
    Minimum Length Synchronizing Sequences of Finite State Machine. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:463-468 [Conf]
  9. Vigyan Singhal, Carl Pixley, Richard L. Rudell, Robert K. Brayton
    The Validity of Retiming Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:316-321 [Conf]
  10. Jun Yuan, Ken Albin, Adnan Aziz, Carl Pixley
    Constraint synthesis for environment modeling in functional verification. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:296-299 [Conf]
  11. In-Ho Moon, Hee-Hwan Kwak, James H. Kukula, Thomas R. Shiple, Carl Pixley
    Simplifying Circuits for Formal Verification Using Parametric Representation. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2002, pp:52-69 [Conf]
  12. In-Ho Moon, Carl Pixley
    Non-miter-based Combinational Equivalence Checking by Comparing BDDs with Different Variable Orders. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2004, pp:144-158 [Conf]
  13. In-Ho Moon, Jae-Young Jang, Gary D. Hachtel, Fabio Somenzi, Jun Yuan, Carl Pixley
    Approximate reachability don't cares for CTL model checking. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:351-358 [Conf]
  14. Carl Pixley, Gary Beihl
    Calculating Resetability and Reset Sequences. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:376-379 [Conf]
  15. Carl Pixley, Vigyan Singhal, Adnan Aziz, Robert K. Brayton
    Multi-level synthesis for safe replaceability. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:442-449 [Conf]
  16. Jun Yuan, Ken Albin, Adnan Aziz, Carl Pixley
    Simplifying Boolean constraint solving for random simulation-vector generation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:123-127 [Conf]
  17. Jun Yuan, Carl Pixley, Adnan Aziz, Ken Albin
    A Framework for Constrained Functional Verification. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:142-145 [Conf]
  18. Jun Yuan, Kurt Shultz, Carl Pixley, Hillel Miller, Adnan Aziz
    Modeling design constraints and biasing in simulation using BDDs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:584-590 [Conf]
  19. Matt Kaufmann, Carl Pixley
    Intertwined Development and Formal Verification of a 60x Bus Model. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:25-30 [Conf]
  20. Carl Pixley, Gary Beihl, Ernesto Pacas-Skewes
    Automatic Derivation of FSM Specification to Implementation Encoding. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:245-249 [Conf]
  21. Vigyan Singhal, Robert K. Brayton, Carl Pixley
    Power-Up Delay for Retiming Digital Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:566-569 [Conf]
  22. Noel R. Strader, Gérard Memmi, Carl Pixley
    Application of Formal Verification to Design Creation and Implementation. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:11- [Conf]
  23. Carl Pixley, Noel R. Strader, W. C. Bruce, Jaehong Park, Matt Kaufmann, Kurt Shultz, Michael Burns, Jainendra Kumar, Jun Yuan, Janet Nguyen
    Commercial Design Verification: Methodology and Tools. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:839-848 [Conf]
  24. Jun Yuan, Ken Albin, Adnan Aziz, Carl Pixley
    Simplifying Constraint Solving in Random Simulation Generation. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:185-190 [Conf]
  25. Carl Pixley, D. Meyers, S. McMaster, A. Chittor
    Designers want proofs - but show me the money. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2004, pp:153-154 [Conf]
  26. Carl Pixley, Kurt Shultz, Jun Yuan
    Integrated Formal and Informal Design Verification of Commercial Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    PDPTA, 1999, pp:1061-1068 [Conf]
  27. Carl Pixley
    An Incremental Garbage Collection Algorithm for Multi-Mutator Systems. [Citation Graph (0, 0)][DBLP]
    Distributed Computing, 1988, v:3, n:1, pp:41-50 [Journal]
  28. Carl Pixley
    Guest Editor's Introduction: Formal Verification of Commercial Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:4, pp:4-5 [Journal]
  29. Carl Pixley, Juan Antonio Carballo
    Panel Summaries. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:4, pp:86-88 [Journal]
  30. Carl Pixley, Sharad Malik
    Guest Editors' Introduction: Exploring Synergies for Design Verification. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:6, pp:461-463 [Journal]
  31. Sandeep K. Shukla, Carl Pixley, Gary Smith
    Guest Editors' Introduction: The True State of the Art of ESL Design. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:5, pp:335-337 [Journal]
  32. Alfred Kölbl, Carl Pixley
    Constructing Efficient Formal Models from High-Level Descriptions Using Symbolic Simulation. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2005, v:33, n:6, pp:645-666 [Journal]
  33. Carl Pixley, Vigyan Singhal
    Model Checking: A Hardware Design Perspective. [Citation Graph (0, 0)][DBLP]
    STTT, 1999, v:2, n:3, pp:288-306 [Journal]
  34. Carl Pixley
    A theory and implementation of sequential hardware equivalence. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:12, pp:1469-1478 [Journal]
  35. Carl Pixley, Seh-Woong Jeong, Gary D. Hachtel
    Exact calculation of synchronizing sequences based on binary decision diagrams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:8, pp:1024-1034 [Journal]
  36. Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K. Brayton
    Theory of safe replacements for sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:2, pp:249-265 [Journal]
  37. Jun Yuan, Adnan Aziz, Carl Pixley, Ken Albin
    Simplifying Boolean constraint solving for random simulation-vector generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:3, pp:412-420 [Journal]
  38. Vigyan Singhal, Carl Pixley, Adnan Aziz, Shaz Qadeer, Robert K. Brayton
    Sequential optimization in the absence of global reset. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:2, pp:222-251 [Journal]
  39. Alfred Koelbl, Jerry R. Burch, Carl Pixley
    Memory Modeling in ESL-RTL Equivalence Checking. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:205-209 [Conf]
  40. In-Ho Moon, Per Bjesse, Carl Pixley
    A compositional approach to the combination of combinational and sequential equivalence checking of circuits without known reset states. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1170-1175 [Conf]

  41. Solver technology for system-level to RTL equivalence checking. [Citation Graph (, )][DBLP]


  42. Exploiting power-up delay for sequential optimization. [Citation Graph (, )][DBLP]


  43. Practical Considerations Concerning HL-to -RT Equivalence Checking. [Citation Graph (, )][DBLP]


Search in 0.025secs, Finished in 0.027secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002