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Zainalabedin Navabi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Bijan Alizadeh, Zainalabedin Navabi
    Property Checking based on Hierarchical Integer Equations. [Citation Graph (0, 0)][DBLP]
    ACSD, 2004, pp:26-35 [Conf]
  2. Masoud Daneshtalab, Ashkan Sobhani, Ali Afzali-Kusha, Omid Fatemi, Zainalabedin Navabi
    NoC Hot Spot minimization Using AntNet Dynamic Routing Algorithm. [Citation Graph (0, 0)][DBLP]
    ASAP, 2006, pp:33-38 [Conf]
  3. Pejman Lotfi-Kamran, Mohammad Hosseinabady, Hamid Shojaei, Mehran Massoumi, Zainalabedin Navabi
    TED+: a data structure for microprocessor verification. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:567-572 [Conf]
  4. Ehsan Atoofian, Zainalabedin Navabi
    A BIST Architecture for FPGA Look-Up Table Testing Reduces Reconfigurations. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:84-89 [Conf]
  5. Hadi Esmaeilzadeh, Saeed Shamshiri, Pooya Saeedi, Zainalabedin Navabi
    ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:236-241 [Conf]
  6. Hamed Farshbaf, Mina Zolfy, Shahrzad Mirkhani, Zainalabedin Navabi
    Fault Simulation for VHDL Based Test Bench and BIST Evaluation. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:396-0 [Conf]
  7. Shahrzad Mirkhani, Meisam Lavasani, Zainalabedin Navabi
    Hierarchical Fault Simulation Using Behavioral and Gate Level Hardware Models. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:374-0 [Conf]
  8. Shahrzad Mirkhani, Zainalabedin Navabi
    Enhancing Fault Simulation Performance by Dynamic Fault Clustering. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:278-283 [Conf]
  9. Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi
    The VPI-Based Combinational IP Core Module-Based Mixed Level Serial Fault Simulation and Test Generation Methodology. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:274-277 [Conf]
  10. Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi
    Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:158-163 [Conf]
  11. Zainalabedin Navabi, Amirhooshang Hashemi, Massoud Eghtesad, Mankuan Michael Vai
    Modeling Timing Behavior of Logic Circuits Using Piecewise Linear Models. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:569-586 [Conf]
  12. Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi
    Using Verilog VPI for Mixed Level Serial Fault Simulation in a Test Generation Environment. [Citation Graph (0, 0)][DBLP]
    Embedded Systems and Applications, 2003, pp:139-143 [Conf]
  13. M. Saneei, Ali Afzali-Kusha, Zainalabedin Navabi
    Sign bit reduction encoding for low power applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:214-217 [Conf]
  14. Mohammad Hosseinabady, Abbas Banaiyan, Mahdi Nazm Bojnordi, Zainalabedin Navabi
    A concurrent testing method for NoC switches. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1171-1176 [Conf]
  15. Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi
    Simultaneous Reduction of Dynamic and Static Power in Scan Structures. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:846-851 [Conf]
  16. Mina Zolfy, Shahrzad Mirkhani, Zainalabedin Navabi
    Adaptation of an event-driven simulation environment to sequentially propagated concurrent fault simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:823- [Conf]
  17. Mohammad Hossein Neishaburi, Mohammad Reza Kakoee, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi
    A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:247-250 [Conf]
  18. Farzin Karimi, Waleed Meleis, Zainalabedin Navabi, Fabrizio Lombardi
    Data Compression for System-on-Chip Testing Using ATE. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:166-176 [Conf]
  19. Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi
    Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:389-397 [Conf]
  20. Shervin Sharifi, Mohammad Hosseinabady, Pedram A. Riahi, Zainalabedin Navabi
    Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:352-360 [Conf]
  21. Naghmeh Karimi, Shahrzad Mirkhani, Zainalabedin Navabi, Fabrizio Lombardi
    RT level reliability enhancement by constructing dynamic TMRS. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:172-175 [Conf]
  22. Mohammad Alisafaee, Safar Hatami, Ehsan Atoofian, Zainalabedin Navabi, Ali Afzali-Kusha
    A low-power scan-path architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5278-5281 [Conf]
  23. Arash Hooshmand, Saeed Shamshiri, Mohammad Alisafaee, Bijan Alizadeh, Pejman Lotfi-Kamran, Mostafa Naderi, Zainalabedin Navabi
    Binary Taylor diagrams: an efficient implementation of Taylor expansion diagrams. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:424-427 [Conf]
  24. Mohammad H. Tehranipour, Zainalabedin Navabi, Seid Mehdi Fakhraie
    An efficient BIST method for testing of embedded SRAMs. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:73-76 [Conf]
  25. Mahnaz Sadoughi Yarandi, Armin Alaghi, Zainalabedin Navabi
    An Optimized BIST Architecture for FPGA Look-Up Table Testing. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:420-421 [Conf]
  26. Masood Dehyadgari, Mohsen Nickray, Ali Afzali-Kusha, Zainalabedin Navabi
    A New Protocol Stack Model for Network on Chip. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:440-441 [Conf]
  27. Bijan Alizadeh, Zainalabedin Navabi
    Using Integer Equations to Check PSL Properties in RT Level Design. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:83-86 [Conf]
  28. Elham Safi, Zohreh Karimi, Maghsoud Abbaspour, Zainalabedin Navabi
    Utilizing Various ADL Facets for Instruction Level CPU Test. [Citation Graph (0, 0)][DBLP]
    MTV, 2003, pp:38-0 [Conf]
  29. Morteza Fayyazi, David R. Kaeli, Zainalabedin Navabi
    Dynamic Input Buffer Allocation (DIBA) for Fault Tolerant Ethernet Packet Switching. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2003, pp:819-823 [Conf]
  30. Mohammad D. Mottaghi, Ali Afzali-Kusha, Zainalabedin Navabi
    ByZFAD: a low switching activity architecture for shift-and-add multipliers. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:179-183 [Conf]
  31. Masoud Daneshtalab, Ali Afzali-Kusha, Ashkan Sobhani, Zainalabedin Navabi, Mohammad D. Mottaghi, Omid Fatemi
    Ant colony based routing architecture for minimizing hot spots in NOCs. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:56-61 [Conf]
  32. Ehsan Atoofian, Zainalabedin Navabi
    A Low Power BIST Architecture for FPGA Look-Up Table Testing. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:394-397 [Conf]
  33. Elham Safi, Reihaneh Saberi, Zohreh Karimi, Zainalabedin Navabi
    Processor Testing Using an ADL Description and Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:186-0 [Conf]
  34. Shervin Sharifi, Mohammad Hosseinabady, Zainalabedin Navabi
    Selective Trigger Scan Architecture for Reducing Power, Time and Data Volume in SoC Testing. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:215-220 [Conf]
  35. Hamid Reza Ghasemi, Zainalabedin Navabi
    An Effective VHDL-AMS Simulation Algorithm with Event Partitioning. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:762-767 [Conf]
  36. Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Pejman Lotfi-Kamran, Zainalabedin Navabi
    A UML Based System Level Failure Rate Assessment Technique for SoC Designs. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:243-248 [Conf]
  37. N. Honarmand, A. Shahabi, H. Sohofi, Maghsoud Abbaspour, Zainalabedin Navabi
    High Level Synthesis of Degradable ASICs Using Virtual Binding. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:311-317 [Conf]
  38. Ehsan Atoofian, Zainalabedin Navabi
    A Test Approach for Look-Up Table Based FPGAs. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2006, v:21, n:1, pp:141-146 [Journal]
  39. Zainalabedin Navabi
    A high-level language for design and modeling of hardware. [Citation Graph (0, 0)][DBLP]
    Journal of Systems and Software, 1992, v:18, n:1, pp:5-18 [Journal]
  40. F. J. Hill, R. E. Swanson, M. Masud, Zainalabedin Navabi
    Structure Specification with a Procedural Hardware Description Language. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1981, v:30, n:2, pp:157-161 [Journal]
  41. F. J. Hill, Zainalabedin Navabi, C. H. Chiang, Duan-Ping Chen, M. Masud
    Hardware Compilation from an RTL to a Storage Logic Array Target. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:3, pp:208-217 [Journal]
  42. Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi
    Instruction-level test methodology for CPU core self-testing. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:4, pp:673-689 [Journal]
  43. Mohammad Hosseinabady, Atefe Dalirsani, Zainalabedin Navabi
    Using the inter- and intra-switch regularity in NoC switch testing. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:361-366 [Conf]
  44. Atefe Dalirsani, Mohammad Hosseinabady, Zainalabedin Navabi
    An Analytical Model for Reliability Evaluation of NoC Architectures. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:49-56 [Conf]
  45. Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Zainalabedin Navabi, Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Giorgio Di Natale
    Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:205-206 [Conf]
  46. Mohammad Reza Kakoee, Hamid Shojaei, Hassan Ghasemzadeh, Marjan Sirjani, Zainalabedin Navabi
    A New Approach for Design and Verification of Transaction Level Models. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3760-3763 [Conf]
  47. A. Shahabi, N. Honarmand, Zainalabedin Navabi
    Programmable Routing Tables for Degradable Torus-Based Networks on Chips. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1065-1068 [Conf]
  48. Hadi Esmaeilzadeh, A. Moghimi, E. Ebrahimi, Caro Lucas, Zainalabedin Navabi, A. M. Fakhraie
    DCim++: a C++ library for object oriented hardware design and distributed simulation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  49. M. Saneei, Ali Afzali-Kusha, Zainalabedin Navabi
    Low-power and low-latency cluster topology for local traffic NoCs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  50. Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi
    Simultaneous Reduction of Dynamic and Static Power in Scan Structures [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  51. Mohammad Hosseinabady, Pejman Lotfi-Kamran, Zainalabedin Navabi
    Low test application time resource binding for behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:2, pp:- [Journal]
  52. Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi
    Scan-Based Structure with Reduced Static and Dynamic Power Consumption. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:3, pp:477-487 [Journal]

  53. BARP-A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs. [Citation Graph (, )][DBLP]


  54. Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Mode. [Citation Graph (, )][DBLP]


  55. Optimizing Parametric BIST Using Bio-inspired Computing Algorithms. [Citation Graph (, )][DBLP]


  56. On-Chip Verification of NoCs Using Assertion Processors. [Citation Graph (, )][DBLP]


  57. Reliability in Application Specific Mesh-Based NoC Architectures. [Citation Graph (, )][DBLP]


  58. A Novel GA-Based High-Level Synthesis Technique to Enhance RT-Level Concurrent Testing. [Citation Graph (, )][DBLP]


  59. Enhanced TED: A New Data Structure for RTL Verification. [Citation Graph (, )][DBLP]


  60. Stall Power Reduction in Pipelined Architecture Processors. [Citation Graph (, )][DBLP]


  61. An NoC Test Strategy Based on Flooding with Power, Test Time and Coverage Considerations. [Citation Graph (, )][DBLP]


  62. A reconfigurable online BIST for combinational hardware using digital neural networks. [Citation Graph (, )][DBLP]


  63. A Configurable Transaction Level Model of a Generic Interconnection Part of Embedded Systems Used in an ESL Design Library. [Citation Graph (, )][DBLP]


  64. APDL: A Processor Description Language For Design Space Exploration of Embedded Processors. [Citation Graph (, )][DBLP]


  65. Combination of Assertion and HSAT Methods For Automated Test Vectors Generation. [Citation Graph (, )][DBLP]


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