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Title:
Author:
Klaus Schneider: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Michael Baldamus, Klaus Schneider
    The BDD Space Complexity of Different Forms of Concurrency. [Citation Graph (0, 0)][DBLP]
    ACSD, 2001, pp:231-0 [Conf]
  2. Klaus Schneider
    Embedding Imperative Synchronous Languages in Interactive Theorem Provers. [Citation Graph (0, 0)][DBLP]
    ACSD, 2001, pp:143-0 [Conf]
  3. Klaus Schneider, Jens Brandt, Tobias Schüle, Thomas Tuerk
    Maximal Causality Analysis. [Citation Graph (0, 0)][DBLP]
    ACSD, 2005, pp:106-115 [Conf]
  4. Klaus Pasemann, Klaus Schneider
    Ein CAD-Anwendungssystem für Autoelektrik. [Citation Graph (0, 0)][DBLP]
    CAD-Fachgespräch, 1977, pp:197-206 [Conf]
  5. Klaus Schneider, Ramayya Kumar, Thomas Kropf
    The FAUST - Prover. [Citation Graph (0, 0)][DBLP]
    CADE, 1992, pp:766-770 [Conf]
  6. Klaus Schneider, Jens Brandt, Tobias Schüle
    Causality analysis of synchronous programs with delayed actions. [Citation Graph (0, 0)][DBLP]
    CASES, 2004, pp:179-189 [Conf]
  7. Klaus Schneider, Ramayya Kumar, Thomas Kropf
    Automating Most Parts of Hardware Proofs in HOL. [Citation Graph (0, 0)][DBLP]
    CAV, 1991, pp:365-375 [Conf]
  8. Thomas Kropf, Ramayya Kumar, Klaus Schneider
    Embedding Hardware Verification Within a Commercial Design Framework. [Citation Graph (0, 0)][DBLP]
    CHARME, 1993, pp:242-257 [Conf]
  9. Klaus Schneider
    Yet another Look at the LTL Model Checking. [Citation Graph (0, 0)][DBLP]
    CHARME, 1999, pp:321-325 [Conf]
  10. Klaus Schneider, Michaela Huhn, George Logothetis
    Validation of Object-Oriented Concurrent Designs by Model Checking. [Citation Graph (0, 0)][DBLP]
    CHARME, 1999, pp:360-364 [Conf]
  11. Klaus Schneider, Ramayya Kumar, Thomas Kropf
    Hardware-Verification using First Order BDDs. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:45-62 [Conf]
  12. Tobias Schüle, Klaus Schneider
    Abstraction of assembler programs for symbolic worst case execution time analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:107-112 [Conf]
  13. Michaela Huhn, Klaus Schneider, Thomas Kropf, George Logothetis
    Verifying Imprecisely Working Arithmetic Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:65-0 [Conf]
  14. George Logothetis, Klaus Schneider
    Abstraction from Counters: An Application on Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:486-493 [Conf]
  15. George Logothetis, Klaus Schneider
    Extending Synchronous Languages for Generating Abstract Real-Time Models. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:795-803 [Conf]
  16. George Logothetis, Klaus Schneider
    Exact High Level WCET Analysis of Synchronous Programs by Symbolic State Space Exploration. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10196-10203 [Conf]
  17. Ralf Reetz, Klaus Schneider, Thomas Kropf
    Formal Specification in VHDL for Hardware Verification. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:257-0 [Conf]
  18. George Logothetis, Klaus Schneider
    A New Approach to the Specification and Verification of Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    ECRTS, 2001, pp:171-0 [Conf]
  19. Klaus Schneider, Viktor K. Sabelfeld
    Introducing Mutual Exclusion in Esterel. [Citation Graph (0, 0)][DBLP]
    Ershov Memorial Conference, 1999, pp:445-459 [Conf]
  20. Jens Brandt, Klaus Schneider
    Dependable Polygon-Processing Algorithms for Safety-Critical Embedded Systems. [Citation Graph (0, 0)][DBLP]
    EUC, 2005, pp:405-417 [Conf]
  21. Klaus Schneider, Thomas Kropf, Ramayya Kumar
    Control Path Oriented Verification of Sequential Generic Circuits with Control and Data Path. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:648-652 [Conf]
  22. Thomas Stauner, Klaus Schneider, Michaela Huhn
    Translating a Visual Description Technique to a Synchronous Language: From DiChartsto PURR. [Citation Graph (0, 0)][DBLP]
    FBT, 1999, pp:223-232 [Conf]
  23. Klaus Schneider, Thomas Kropf
    The C@S System. [Citation Graph (0, 0)][DBLP]
    Formal Hardware Verification, 1997, pp:248-329 [Conf]
  24. Klaus Schneider
    Model Checking on Product Structures. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1998, pp:483-500 [Conf]
  25. Klaus Schneider, Thomas Kropf
    A Unified Approach for Combining Different Formalisms for Hardware Verification. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1996, pp:202-217 [Conf]
  26. Andreas Morgenstern, Klaus Schneider
    A unified model checking framework for the supervisor synthesis problem. [Citation Graph (0, 0)][DBLP]
    GALOP, 2005, pp:140-156 [Conf]
  27. Raffaella Gentilini, Klaus Schneider, Alexander Dreyer
    Three-valued automated reasoning on analog properties. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:485-488 [Conf]
  28. Tobias Schüle, Klaus Schneider
    Verification of Data Paths Using Unbounded Integers: Automata Strike Back. [Citation Graph (0, 0)][DBLP]
    Haifa Verification Conference, 2006, pp:65-80 [Conf]
  29. Thomas Tuerk, Klaus Schneider, Mike Gordon
    Model Checking PSL Using HOL and SMV. [Citation Graph (0, 0)][DBLP]
    Haifa Verification Conference, 2006, pp:1-15 [Conf]
  30. Jens Brandt, Klaus Schneider
    Using Three-Valued Logic to Specify and Verify Algorithms of Computational Geometry. [Citation Graph (0, 0)][DBLP]
    ICFEM, 2005, pp:405-420 [Conf]
  31. Andreas Morgenstern, Klaus Schneider
    Synthesizing deterministic controllers in supervisory control. [Citation Graph (0, 0)][DBLP]
    ICINCO, 2005, pp:24-31 [Conf]
  32. O. Sawodny, A. Hildebrandt, K. Schneider
    Control design for the rotation of crane loads for boom cranes. [Citation Graph (0, 0)][DBLP]
    ICRA, 2003, pp:2182-2187 [Conf]
  33. Klaus Schneider
    A Verified Hardware Synthesis of Esterel Programs. [Citation Graph (0, 0)][DBLP]
    DIPES, 2000, pp:205-214 [Conf]
  34. Klaus Schneider, Michaela Huhn
    Comparing Model Checking and Term Rewriting for the Verification of an Embedded System. [Citation Graph (0, 0)][DBLP]
    DIPES, 1998, pp:129-138 [Conf]
  35. Klaus Schneider
    Improving Automata Generation for Linear Temporal Logic by Considering the Automaton Hierarchy. [Citation Graph (0, 0)][DBLP]
    LPAR, 2001, pp:39-54 [Conf]
  36. Tobias Schüle, Klaus Schneider
    Exact Runtime Analysis Using Automata-Based Symbolic Simulation. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2003, pp:153-162 [Conf]
  37. Tobias Schüle, Klaus Schneider
    Bounded model checking of infinite state systems: exploiting the automata hierarchy. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2004, pp:17-26 [Conf]
  38. Tobias Schüle, Klaus Schneider
    Three-valued logic in bounded model checking. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2005, pp:177-186 [Conf]
  39. Roberto Ziller, Klaus Schneider
    A Generalised Approach to Supervisor Synthesis. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2003, pp:217-226 [Conf]
  40. Klaus Schneider
    Ein System-Diagnoseprozessor für zentralen und dezentralen Einsatz in Prozeßrechner-Systemen. [Citation Graph (0, 0)][DBLP]
    Fachtagung Prozessrechner, 1981, pp:186-195 [Conf]
  41. George Logothetis, Klaus Schneider, C. Metzler
    Generating Formal Models for Real-Time Verification by Exact Low-Level Runtime Analysis of Synchronous Programs. [Citation Graph (0, 0)][DBLP]
    RTSS, 2003, pp:256-264 [Conf]
  42. George Logothetis, Klaus Schneider, C. Metzler
    Runtime Analysis of Synchronous Programs for Low-Level Real-Time Verification. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:211-216 [Conf]
  43. Tobias Schüle, Klaus Schneider
    Global vs. Local Model Checking: A Comparison of Verification Techniques for Infinite State Systems. [Citation Graph (0, 0)][DBLP]
    SEFM, 2004, pp:67-76 [Conf]
  44. George Logothetis, Klaus Schneider
    Symbolic Model Checking of Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    TIME, 2001, pp:214-223 [Conf]
  45. Thomas Kropf, Klaus Schneider, Ramayya Kumar
    A Formal Framework for High Level Synthesis. [Citation Graph (0, 0)][DBLP]
    TPCD, 1994, pp:223-238 [Conf]
  46. Dirk Eisenbiegler, Klaus Schneider, Ramayya Kumar
    A Functional Approach for Formalizing Regular Hardware Structures. [Citation Graph (0, 0)][DBLP]
    HUG, 1993, pp:101-114 [Conf]
  47. Ramayya Kumar, Thomas Kropf, Klaus Schneider
    Integrating a First-Order Automatic Prover in the HOL Environment. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1991, pp:170-176 [Conf]
  48. Ramayya Kumar, Thomas Kropf, Klaus Schneider
    First Steps Towards Automating Hardware Proofs in HOL. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1991, pp:190-193 [Conf]
  49. Klaus Schneider
    Proving the Equivalence of Microstep and Macrostep Semantics. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 2002, pp:314-331 [Conf]
  50. Klaus Schneider, Dirk W. Hoffmann
    A HOL Conversion for Translating Linear Time Temporal Logic to omega-Automata. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1999, pp:255-272 [Conf]
  51. Klaus Schneider, Ramayya Kumar, Thomas Kropf
    Efficient Representation and Computation of Tableau Proofs. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1992, pp:39-57 [Conf]
  52. Klaus Schneider, Ramayya Kumar, Thomas Kropf
    Modelling Generic Hardware Structures by Abstract Datatypes. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1992, pp:165-175 [Conf]
  53. Klaus Schneider, Ramayya Kumar, Thomas Kropf
    Alternative Proof Procedures for Finite-State Machines in Higher-Order Logic. [Citation Graph (0, 0)][DBLP]
    HUG, 1993, pp:213-226 [Conf]
  54. Klaus Schneider, Ramayya Kumar, Thomas Kropf
    Eliminating Higher-Order Quantifiers to Obtain Decision Procedures for Hardware Verification. [Citation Graph (0, 0)][DBLP]
    HUG, 1993, pp:385-398 [Conf]
  55. Klaus Schneider, Ramayya Kumar, Thomas Kropf
    Automating Verification by Functional Abstraction at the System Level. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1994, pp:391-406 [Conf]
  56. Thomas Tuerk, Klaus Schneider
    From PSL to LTL: A Formal Validation in HOL. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 2005, pp:342-357 [Conf]
  57. Klaus Schneider, Ramayya Kumar, Thomas Kropf
    Structurein Hardware Proofs: Fist Steps Towards Automation in a Higher-Order Environment. [Citation Graph (0, 0)][DBLP]
    VLSI, 1991, pp:81-90 [Conf]
  58. Ramayya Kumar, Thomas Kropf, Klaus Schneider
    Formal synthesis of circuits with a simple handshake protocol. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:255-259 [Conf]
  59. Michael Baldamus, Klaus Schneider, Michael Wenz, Roberto Ziller
    Can American Checkers be Solved by Means of Symbolic Model Checking? [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2001, v:43, n:, pp:- [Journal]
  60. Klaus Schneider, Jens Brandt, Tobias Schüle
    A Verified Compiler for Synchronous Programs with Local Declarations. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2006, v:153, n:4, pp:71-97 [Journal]
  61. Klaus Schneider, Ramayya Kumar, Thomas Kropf
    Accelerating Tableaux Proofs Using Compact Representations. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1994, v:5, n:1/2, pp:145-176 [Journal]
  62. Ramayya Kumar, Klaus Schneider, Thomas Kropf
    Structuring and Automating Hardware Proofs in a Higher-Order Theorem-Proving Environment. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1993, v:2, n:2, pp:165-223 [Journal]
  63. Michael Baldamus, Klaus Schneider
    The BDD Space Complexity of Different Forms of Concurrency. [Citation Graph (0, 0)][DBLP]
    Fundam. Inform., 2002, v:50, n:2, pp:111-133 [Journal]
  64. Klaus Pasemann, Klaus Schneider, Ernst Vöge
    Das grafische Ausgabesystem am VW-Prozeß-Leit-System (PLS). [Citation Graph (0, 0)][DBLP]
    Elektronische Rechenanlagen, 1976, v:18, n:5, pp:241-245 [Journal]
  65. Roberto Ziller, Klaus Schneider
    Combining supervisor synthesis and model checking. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2005, v:4, n:2, pp:331-362 [Journal]
  66. Klaus Schneider, Jens Brandt, Eric Vecchié
    Modular Compilation of Synchronous Programs. [Citation Graph (0, 0)][DBLP]
    DIPES, 2006, pp:75-84 [Conf]
  67. Raffaella Gentilini, Klaus Schneider, B. Mishra
    Successive Abstractions of Hybrid Automata for Monotonic CTL Model Checking. [Citation Graph (0, 0)][DBLP]
    LFCS, 2007, pp:224-240 [Conf]
  68. Klaus Schneider, Jens Brandt, Eric Vecchié
    Efficient code generation from synchronous programs. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2006, pp:165-174 [Conf]
  69. Tobias Schüle, Klaus Schneider
    Bounded model checking of infinite state systems. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2007, v:30, n:1, pp:51-81 [Journal]

  70. Predicting Events for the Simulation of Hybrid Systems. [Citation Graph (, )][DBLP]


  71. Desynchronizing Synchronous Programs by Modes. [Citation Graph (, )][DBLP]


  72. Performing causality analysis by bounded model checking. [Citation Graph (, )][DBLP]


  73. Separate compilation and execution of imperative synchronous modules. [Citation Graph (, )][DBLP]


  74. Multithreaded code from synchronous programs: Extracting independent threads for OpenMP. [Citation Graph (, )][DBLP]


  75. A Uniform Approach to Three-Valued Semantics for µ-Calculus on Abstractions of Hybrid Automata. [Citation Graph (, )][DBLP]


  76. From synchronous programs to symbolic representations of hybrid systems. [Citation Graph (, )][DBLP]


  77. Translating concurrent action oriented specifications to synchronous guarded actions. [Citation Graph (, )][DBLP]


  78. Formal Reasoning About Causality Analysis. [Citation Graph (, )][DBLP]


  79. From LTL to Symbolically Represented Deterministic Automata. [Citation Graph (, )][DBLP]


  80. Property Driven Three-Valued Model Checking on Hybrid Automata. [Citation Graph (, )][DBLP]


  81. How Different are Esterel and SystemC?. [Citation Graph (, )][DBLP]


  82. System Description Aspects as Syntactic Sugar. [Citation Graph (, )][DBLP]


  83. Exact Low-Level Runtime Analysis of Synchronous Programs for Formal Verification of Real-Time Systems. [Citation Graph (, )][DBLP]


  84. Online Exercise System - A Web-based Tool for Administration and Automatic Correction of Exercises. [Citation Graph (, )][DBLP]


  85. Exploiting the Temporal Logic Hierarchy and the Non-Confluence Property for Efficient LTL Synthesis [Citation Graph (, )][DBLP]


  86. Preface. [Citation Graph (, )][DBLP]


  87. Approximated Reachability on Hybrid Automata: Falsification meets Certification. [Citation Graph (, )][DBLP]


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