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Author:
Robert K. Brayton: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yinghua Li, Alex Kondratyev, Robert K. Brayton
    Gaining Predictability and Noise Immunity in Global Interconnects. [Citation Graph (0, 0)][DBLP]
    ACSD, 2005, pp:176-185 [Conf]
  2. Zhongcheng Li, Yinghua Min, Robert K. Brayton
    A New Low-Cost Method for Identifying Untestable Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:76-81 [Conf]
  3. Rajeev Alur, Robert K. Brayton, Thomas A. Henzinger, Shaz Qadeer, Sriram K. Rajamani
    Partial-Order Reduction in Symbolic State Space Exploration. [Citation Graph (0, 0)][DBLP]
    CAV, 1997, pp:340-351 [Conf]
  4. Adnan Aziz, Felice Balarin, Robert K. Brayton, M. D. DiBenedetto, Alexander Saldanha
    Supervisory Control of Finite State Machines. [Citation Graph (0, 0)][DBLP]
    CAV, 1995, pp:279-292 [Conf]
  5. Adnan Aziz, Kumud Sanwal, Vigyan Singhal, Robert K. Brayton
    Verifying Continuous Time Markov Chains. [Citation Graph (0, 0)][DBLP]
    CAV, 1996, pp:269-276 [Conf]
  6. Robert K. Brayton
    Logic Synthesis and Design Verification. [Citation Graph (0, 0)][DBLP]
    CAV, 1993, pp:1-2 [Conf]
  7. Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa
    VIS: A System for Verification and Synthesis. [Citation Graph (0, 0)][DBLP]
    CAV, 1996, pp:428-432 [Conf]
  8. Ramin Hojati, Robert K. Brayton
    Automatic Datapath Abstraction In Hardware Systems. [Citation Graph (0, 0)][DBLP]
    CAV, 1995, pp:98-113 [Conf]
  9. Ramin Hojati, Robert K. Brayton, Robert P. Kurshan
    BDD-Based Debugging Of Design Using Language Containment and Fair CTL. [Citation Graph (0, 0)][DBLP]
    CAV, 1993, pp:41-58 [Conf]
  10. Ramin Hojati, Robert B. Mueller-Thuns, Robert K. Brayton
    Improving Language Containment Using Fairness Graphs. [Citation Graph (0, 0)][DBLP]
    CAV, 1994, pp:391-403 [Conf]
  11. Ramin Hojati, Hervé J. Touati, Robert P. Kurshan, Robert K. Brayton
    Efficient omega-Regular Language Containment. [Citation Graph (0, 0)][DBLP]
    CAV, 1992, pp:396-409 [Conf]
  12. Adrian J. Isles, Ramin Hojati, Robert K. Brayton
    Computing Reachable Control States of Systems Modeled with Uninterpreted Functions and Infinite Memory. [Citation Graph (0, 0)][DBLP]
    CAV, 1998, pp:256-267 [Conf]
  13. Jie-Hong Roland Jiang, Robert K. Brayton
    Functional Dependency for Verification Reduction. [Citation Graph (0, 0)][DBLP]
    CAV, 2004, pp:268-280 [Conf]
  14. Sriram C. Krishnan, Anuj Puri, Robert K. Brayton, Pravin Varaiya
    The Rabin Index and Chain Automata, with Applications to Automatas and Games. [Citation Graph (0, 0)][DBLP]
    CAV, 1995, pp:253-266 [Conf]
  15. William K. C. Lam, Robert K. Brayton
    Alternating RQ Timed Automata. [Citation Graph (0, 0)][DBLP]
    CAV, 1993, pp:237-252 [Conf]
  16. William K. C. Lam, Robert K. Brayton
    Criteria for the Simple Path Property in Timed Automata. [Citation Graph (0, 0)][DBLP]
    CAV, 1994, pp:27-40 [Conf]
  17. Gurmeet Singh Manku, Ramin Hojati, Robert K. Brayton
    Structural Symmetry and Model Checking. [Citation Graph (0, 0)][DBLP]
    CAV, 1998, pp:159-171 [Conf]
  18. Thomas R. Shiple, Massimiliano Chiodo, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton
    Automatic Reduction in CTL Compositional Model Checking. [Citation Graph (0, 0)][DBLP]
    CAV, 1992, pp:234-247 [Conf]
  19. Serdar Tasiran, Robert K. Brayton
    STARI: A Case Study in Compositional and Hierarchical Timing Verification. [Citation Graph (0, 0)][DBLP]
    CAV, 1997, pp:191-201 [Conf]
  20. Serdar Tasiran, Ramin Hojati, Robert K. Brayton
    Language containment of non-deterministic omega-automata. [Citation Graph (0, 0)][DBLP]
    CHARME, 1995, pp:261-277 [Conf]
  21. Massimo Baleani, Frank Gennari, Yunjian Jiang, Yatish Patel, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:151-156 [Conf]
  22. Yunjian Jiang, Robert K. Brayton
    Logic optimization and code generation for embedded control applications. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:225-229 [Conf]
  23. Serdar Tasiran, Rajeev Alur, Robert P. Kurshan, Robert K. Brayton
    Verifying Abstractions of Timed Systems. [Citation Graph (0, 0)][DBLP]
    CONCUR, 1996, pp:546-562 [Conf]
  24. Adnan Aziz, Serdar Tasiran, Robert K. Brayton
    BDD Variable Ordering for Interacting Finite State Machines. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:283-288 [Conf]
  25. Adnan Aziz, Felice Balarin, Szu-Tsung Cheng, Ramin Hojati, Timothy Kam, Sriram C. Krishnan, Rajeev K. Ranjan, Thomas R. Shiple, Vigyan Singhal, Serdar Tasiran, Huey-Yih Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    HSIS: A BDD-Based Environment for Formal Verification. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:454-459 [Conf]
  26. Ramin Hojati, Thomas R. Shiple, Robert K. Brayton, Robert P. Kurshan
    A Unified Approach to Language Containment and Fair CTL Model Checking. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:475-481 [Conf]
  27. Yunjian Jiang, Robert K. Brayton
    Software synthesis from synchronous specifications using logic simulation techniques. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:319-324 [Conf]
  28. Yunjian Jiang, Slobodan Matic, Robert K. Brayton
    Generalized cofactoring for logic function evaluation. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:155-158 [Conf]
  29. Dirk-Jan Jongeneel, Yosinori Watanabe, Robert K. Brayton, Ralph H. J. M. Otten
    Area and search space control for technology mapping. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:86-91 [Conf]
  30. Timothy Kam, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    A Fully Implicit Algorithm for Exact State Minimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:684-690 [Conf]
  31. Sunil P. Khatri, Amit Mehrotra, Robert K. Brayton, Ralph H. J. M. Otten, Alberto L. Sangiovanni-Vincentelli
    A Novel VLSI Layout Fabric for Deep Sub-Micron Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:491-496 [Conf]
  32. Sunil P. Khatri, Amit Narayan, Sriram C. Krishnan, Kenneth L. McMillan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Engineering Change in a Non-Deterministic FSM Setting. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:451-456 [Conf]
  33. Yuji Kukimoto, Robert K. Brayton
    Exact Required Time Analysis via False Path Detection. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:220-225 [Conf]
  34. Yuji Kukimoto, Robert K. Brayton
    Hierarchical Functional Timing Analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:580-585 [Conf]
  35. Yuji Kukimoto, Robert K. Brayton, Prashant Sawkar
    Delay-Optimal Technology Mapping by DAG Covering. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:348-351 [Conf]
  36. William K. C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Circuit Delay Models and Their Exact Computation Using Timed Boolean Functions. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:128-134 [Conf]
  37. William K. C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Exact Minimum Cycle Times for Finite State Machines. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:100-105 [Conf]
  38. William K. C. Lam, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Delay Fault Coverage and Performance Tradeoffs. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:446-452 [Conf]
  39. Luciano Lavagno, Cho W. Moon, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Solving the State Assignment Problem for Signal Transition Graphs. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:568-572 [Conf]
  40. Fan Mo, Robert K. Brayton
    River PLAs: a regular circuit structure. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:201-206 [Conf]
  41. Fan Mo, Robert K. Brayton
    A timing-driven module-based chip design flow. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:67-70 [Conf]
  42. Abdul A. Malik, Robert K. Brayton, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
    Reduced Offsets for Two-Level Multi-Valued Logic Minimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:290-296 [Conf]
  43. Yusuke Matsunaga, Patrick C. McGeer, Robert K. Brayton
    On Computing the Transitive Closure of a State Transition Relation. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:260-265 [Conf]
  44. Patrick C. McGeer, Robert K. Brayton
    Efficient Prime Factorization of Logic Expressions. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:221-225 [Conf]
  45. Patrick C. McGeer, Robert K. Brayton
    Efficient Algorithms for Computing the Longest Viable Path in a Combinational Network. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:561-567 [Conf]
  46. Patrick C. McGeer, Robert K. Brayton
    Timing Analysis in Precharge/Unate Networks. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:124-129 [Conf]
  47. Patrick C. McGeer, Jagesh V. Sanghavi, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Espresso-Signature: A New Exact Minimizer for Logic Functions. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:618-624 [Conf]
  48. Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton
    DAG-aware AIG rewriting a fresh look at combinational logic synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:532-535 [Conf]
  49. Cho W. Moon, Robert K. Brayton
    Elimination of Dynamic hazards by Factoring. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:7-13 [Conf]
  50. Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    An Improved Synthesis Algorithm for Multiplexor-Based PGA's. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:380-386 [Conf]
  51. Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Sequential Synthesis for Table Look Up Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:224-229 [Conf]
  52. Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Optimum Functional Decomposition Using Encoding. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:408-414 [Conf]
  53. Rajeev Murgai, Yoshihito Nishizaki, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Logic Synthesis for Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:620-625 [Conf]
  54. Ralph H. J. M. Otten, Robert K. Brayton
    Planning for Performance. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:122-127 [Conf]
  55. Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Equivalence of Robust Delay-Fault and Single Stuck-Fault Test Generation. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:173-176 [Conf]
  56. Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Circuit Structure Relations to Redundancy and Delay: The KMS Algorithm Revisited. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:245-248 [Conf]
  57. Alexander Saldanha, Heather Harkness, Patrick C. McGeer, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Performance Optimization Using Exact Sensitization. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:425-429 [Conf]
  58. Alexander Saldanha, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    A Framework for Satisfying Input and Output Encoding Constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:170-175 [Conf]
  59. Alexander Saldanha, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Multi-level Logic Simplification Using Don't Cares and Filters. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:277-282 [Conf]
  60. Jagesh V. Sanghavi, Rajeev K. Ranjan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    High Performance BDD Package By Exploiting Memory Hiercharchy. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:635-640 [Conf]
  61. Hamid Savoj, Robert K. Brayton
    The Use of Observability and External Don't Cares for the Simplification of Multi-Level Networks. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:297-301 [Conf]
  62. Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Resynthesis of Multi-Phase Pipelines. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:490-496 [Conf]
  63. Narendra V. Shenoy, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    On the Temporal Equivalence of Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:405-409 [Conf]
  64. Thomas R. Shiple, Ramin Hojati, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton
    Heuristic Minimization of BDDs Using Don't Cares. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:225-231 [Conf]
  65. Vigyan Singhal, Carl Pixley, Richard L. Rudell, Robert K. Brayton
    The Validity of Retiming Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:316-321 [Conf]
  66. Abdallah Tabbara, Robert K. Brayton, A. Richard Newton
    Retiming for DSM with Area-Delay Trade-Offs and Delay Constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:725-730 [Conf]
  67. Huey-Yih Wang, Robert K. Brayton
    Permissible Observability Relations in FSM Networks. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:677-683 [Conf]
  68. Jin S. Zhang, Alan Mishchenko, Robert K. Brayton, Malgorzata Chrzanowska-Jeske
    Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:510-515 [Conf]
  69. Evguenii I. Goldberg, Yuji Kukimoto, Robert K. Brayton
    Combinational Verification based on High-Level Functional Specifications. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:803-0 [Conf]
  70. Evguenii I. Goldberg, Mukul R. Prasad, Robert K. Brayton
    Using SAT for combinational equivalence checking. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:114-121 [Conf]
  71. Evguenii I. Goldberg, Mukul R. Prasad, Robert K. Brayton
    Using Problem Symmetry in Search Based Satisfiability Algorithms. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:134-141 [Conf]
  72. Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton
    Reducing Multi-Valued Algebraic Operations to Binary. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10752-10757 [Conf]
  73. Alan Mishchenko, Robert K. Brayton
    SAT-Based Complete Don't-Care Computation for Network Optimization. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:412-417 [Conf]
  74. Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Tiziano Villa, Nina Yevtushenko
    Efficient Solution of Language Equations Using Partitioned Representations. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:418-423 [Conf]
  75. Rajeev K. Ranjan, Vigyan Singhal, Fabio Somenzi, Robert K. Brayton
    Using Combinational Verification for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:138-144 [Conf]
  76. Nina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alexandre Petrenko, Alberto L. Sangiovanni-Vincentelli
    Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11154-11155 [Conf]
  77. Yosinori Watanabe, Robert K. Brayton
    State Minimization of Pseudo Non-Deterministic FSM's. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:184-191 [Conf]
  78. Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa
    VIS. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1996, pp:248-256 [Conf]
  79. Ramin Hojati, Adrian J. Isles, Desmond Kirkpatrick, Robert K. Brayton
    Verification Using Uninterpreted Functions and Finite Instantiations. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1996, pp:218-232 [Conf]
  80. Jawahar Jain, Amit Narayan, C. Coelho, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton, Masahiro Fujita
    Decomposition Techniques for Efficient ROBDD Construction. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1996, pp:419-434 [Conf]
  81. Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton
    Improvements to technology mapping for LUT-based FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2006, pp:41-49 [Conf]
  82. Tiziano Villa, Svetlana Zharikova, Nina Yevtushenko, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    A new algorithm for the largest compositionally progressive solution of synchronous language equations. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:441-444 [Conf]
  83. Adnan Aziz, Vigyan Singhal, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Equivalences for Fair Kripke Structures. [Citation Graph (0, 0)][DBLP]
    ICALP, 1994, pp:364-375 [Conf]
  84. Adnan Aziz, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Sequential synthesis using S1S. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:612-617 [Conf]
  85. Robert K. Brayton
    Compatible Observability Don't Cares Revisited. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:618-0 [Conf]
  86. Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Xinning Wang, Timothy Kam
    Reducing structural bias in technology mapping. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:519-526 [Conf]
  87. Satrajit Chatterjee, Robert K. Brayton
    A new incremental placement algorithm and its application to congestion-aware divisor extraction. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:541-548 [Conf]
  88. Massimiliano Chiodo, Thomas R. Shiple, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton
    Automatic compositional minimization in CTL model checking. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:172-178 [Conf]
  89. Evguenii I. Goldberg, Luca P. Carloni, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Negative thinking by incremental problem solving: application to unate covering. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:91-98 [Conf]
  90. Evguenii I. Goldberg, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    A fast and robust exact algorithm for face embedding. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:296-303 [Conf]
  91. Wilsin Gosti, Amit Narayan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Wireplanning in logic synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:26-33 [Conf]
  92. Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton
    On breakable cyclic definitions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:411-418 [Conf]
  93. Yunjian Jiang, Robert K. Brayton
    Don't Cares and Multi-Valued Logic Network Minimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:520-525 [Conf]
  94. Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Cross-Talk Immune VLSI Design Using a Network of PLAs Embedded in a Regular Layout Fabric. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:412-418 [Conf]
  95. Yuji Kukimoto, Robert K. Brayton
    Timing-safe false path removal for combinational modules. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:544-550 [Conf]
  96. Andreas Kuehlmann, Kenneth L. McMillan, Robert K. Brayton
    Probabilistic state space search. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:574-579 [Conf]
  97. Yuji Kukimoto, Masahiro Fujita, Robert K. Brayton
    A redesign technique for combinational circuits based on gate reconnections. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:632-637 [Conf]
  98. Yuji Kukimoto, Wilsin Gosti, Alexander Saldanha, Robert K. Brayton
    Approximate timing analysis of combinational circuits under the XBD0 model. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:176-181 [Conf]
  99. Fan Mo, Robert K. Brayton
    Whirlpool PLAs: a regular logic structure and their synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:543-550 [Conf]
  100. William K. C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Valid clocking in wavepipelined circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:518-525 [Conf]
  101. Luciano Lavagno, Sharad Malik, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    MIS-MV: Optimization of Multi-Level Logic with Multiple-Valued Inputs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:560-563 [Conf]
  102. Yinghua Li, Alex Kondratyev, Robert K. Brayton
    Synthesis methodology for built-in at-speed testing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:183-188 [Conf]
  103. Sharad Malik, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Performance Optimization of Pipelined Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:410-413 [Conf]
  104. Alan Mishchenko, Robert K. Brayton
    Simplification of non-deterministic multi-valued networks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:557-562 [Conf]
  105. Alan Mishchenko, Robert K. Brayton
    A Theory of Non-Deterministic Networks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:709-717 [Conf]
  106. Fan Mo, Abdallah Tabbara, Robert K. Brayton
    A Force-Directed Macro-Cell Placer. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:177-180 [Conf]
  107. Fan Mo, Abdallah Tabbara, Robert K. Brayton
    A Force-Directed Maze Router. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:404-407 [Conf]
  108. Amit Mehrotra, Shaz Qadeer, Vigyan Singhal, Robert K. Brayton, Adnan Aziz, Alberto L. Sangiovanni-Vincentelli
    Sequential optimisation without state space exploration. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:208-215 [Conf]
  109. Cho W. Moon, Paul R. Stephan, Robert K. Brayton
    Synthesis of Hazard-Free Asynchronous Circuits from Graphical Specifications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:322-325 [Conf]
  110. Patrick C. McGeer, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli, Sartaj Sahni
    Performance Enhancement through the Generalized Bypass Transform. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:184-187 [Conf]
  111. Patrick C. McGeer, Alexander Saldanha, Paul R. Stephan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Timing Analysis and Delay-Fault Test Generation using Path-Recursive Functions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:180-183 [Conf]
  112. Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    On Clustering for Minimum Delay/Area. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:6-9 [Conf]
  113. Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Cube-packing and two-level minimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:115-122 [Conf]
  114. Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Improved Logic Synthesis Algorithms for Table Look Up Architectures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:564-567 [Conf]
  115. Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Performance Directed Synthesis for Table Look Up Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:572-575 [Conf]
  116. Amit Narayan, Adrian J. Isles, Jawahar Jain, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Reachability analysis using partitioned-ROBDDs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:388-393 [Conf]
  117. Carl Pixley, Vigyan Singhal, Adnan Aziz, Robert K. Brayton
    Multi-level synthesis for safe replaceability. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:442-449 [Conf]
  118. Rajeev K. Ranjan, Vigyan Singhal, Fabio Somenzi, Robert K. Brayton
    On the optimization power of retiming and resynthesis transformations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:402-407 [Conf]
  119. Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli, Kwang-Ting Cheng
    Timing Optimization with Testability Considerations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:460-463 [Conf]
  120. Hamid Savoj, Robert K. Brayton
    Observability Relations and Observability Don't Cares. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:518-521 [Conf]
  121. Hamid Savoj, Robert K. Brayton, Hervé J. Touati
    Extracting Local Don't Cares for Network Optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:514-517 [Conf]
  122. Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Graph algorithms for clock schedule optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:132-136 [Conf]
  123. Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Minimum padding to satisfy short path constraints. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:156-161 [Conf]
  124. Vigyan Singhal, Sharad Malik, Robert K. Brayton
    The case for retiming with explicit reset circuitry. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:618-625 [Conf]
  125. Subarnarekha Sinha, Robert K. Brayton
    Implementation and use of SPFDs in optimizing Boolean networks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:103-110 [Conf]
  126. Subarnarekha Sinha, Andreas Kuehlmann, Robert K. Brayton
    Sequential SPFDs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:84-90 [Conf]
  127. Subarnarekha Sinha, Alan Mishchenko, Robert K. Brayton
    Topologically constrained logic synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:679-686 [Conf]
  128. Arvind Srinivasan, Timothy Kam, Sharad Malik, Robert K. Brayton
    Algorithms for Discrete Function Manipulation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:92-95 [Conf]
  129. Gitanjali Swamy, Robert K. Brayton
    Incremental formal design verification. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:458-465 [Conf]
  130. Hervé J. Touati, Hamid Savoj, Robert K. Brayton
    Delay Optimization of Combinational Logic Circuits By Clustering and Partial Collapsing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:188-191 [Conf]
  131. Hervé J. Touati, Hamid Savoj, Bill Lin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Implicit State Enumeration of Finite State Machines Using BDDs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:130-133 [Conf]
  132. Huey-Yih Wang, Robert K. Brayton
    Input don't care sequences in FSM networks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:321-328 [Conf]
  133. Huey-Yih Wang, Robert K. Brayton
    Multi-level logic optimization of FSM networks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:728-735 [Conf]
  134. Nina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alexandre Petrenko, Alberto L. Sangiovanni-Vincentelli
    Solution of Parallel Language Equations for Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:103-0 [Conf]
  135. Yosinori Watanabe, Robert K. Brayton
    The maximum set of permissible behaviors for FSM networks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:316-320 [Conf]
  136. Yosinori Watanabe, Robert K. Brayton
    Heuristic Minimazation of Multiple-Valued Relations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:126-129 [Conf]
  137. Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton, Niklas Eén
    Improvements to combinational equivalence checking. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:836-843 [Conf]
  138. Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton
    Factor cuts. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:143-150 [Conf]
  139. Adnan Aziz, Vigyan Singhal, Gitanjali Swamy, Robert K. Brayton
    Minimizing Interacting Finite State Machines: A Compositional Approach to Language to Containment. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:255-261 [Conf]
  140. Paul T. Gutwin, Patrick C. McGeer, Robert K. Brayton
    Delay Prediction for Technology-Independent Logic Equations. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:468-471 [Conf]
  141. Ramin Hojati, Sriram C. Krishnan, Robert K. Brayton
    Early Quantification and Partitioned Transition Relations. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:12-19 [Conf]
  142. Timothy Kam, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Implicit state minimization of non-deterministic FSMs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:250-257 [Conf]
  143. William K. C. Lam, Robert K. Brayton
    On Relationship Between ITE and BDD. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:448-451 [Conf]
  144. Zhongcheng Li, Yuhong Zhao, Yinghua Min, Robert K. Brayton
    Timed Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:352-357 [Conf]
  145. Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Some Results on the Complexity of Boolean Functions for Table Look Up Architectures. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:505-512 [Conf]
  146. Abdul A. Malik, David Harrison, Robert K. Brayton
    Three-Level Decomposition with Application to PLDs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:628-633 [Conf]
  147. Fan Mo, Abdallah Tabbara, Robert K. Brayton
    A Timing-Driven Macro-Cell Placement Algorithm. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:322-327 [Conf]
  148. Shaz Qadeer, Robert K. Brayton, Vigyan Singhal
    Latch Redundancy Removal Without Global Reset. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:432-439 [Conf]
  149. Rajeev K. Ranjan, Wilsin Gosti, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Dynamic Reordering in a Breadth-First Manipulation Based BDD Package: Challenges and Solutions. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:344-351 [Conf]
  150. Rajeev K. Ranjan, Jagesh V. Sanghavi, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Binary decision diagrams on network of workstation. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:358-364 [Conf]
  151. Ellen Sentovich, Robert K. Brayton
    An Exact Optimization of Two-Level Acyclic Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:242-249 [Conf]
  152. Ellen Sentovich, Kanwar Jit Singh, Cho W. Moon, Hamid Savoj, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Sequential Circuit Design Using Synthesis and Optimization. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:328-333 [Conf]
  153. Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Retiming of Circuits with Single Phase Transparent Latches. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:86-89 [Conf]
  154. Vigyan Singhal, Yosinori Watanabe, Robert K. Brayton
    Heuristic Minimization of Synchronous Relations. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:428-433 [Conf]
  155. Subarnarekha Sinha, Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:494-503 [Conf]
  156. Paul R. Stephan, Robert K. Brayton
    Physically Realizable Gate Models. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:442-445 [Conf]
  157. Gitanjali Swamy, Robert K. Brayton, Vigyan Singhal
    Incremental methods for FSM traversal. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:590-0 [Conf]
  158. Yosinori Watanabe, Robert K. Brayton
    Incremental Synthesis for Engineering Changes. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:40-43 [Conf]
  159. Yosinori Watanabe, Lisa Guerra, Robert K. Brayton
    Logic Optimization with Multi-Output Gates. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:416-420 [Conf]
  160. Luca P. Carloni, Evguenii I. Goldberg, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Aura II: Combining Negative Thinking and Branch-and-Bound in Unate Covering Problems. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:346-361 [Conf]
  161. Sriram C. Krishnan, Anuj Puri, Robert K. Brayton
    Deterministic w Automata vis-a-vis Deterministic Buchi Automata. [Citation Graph (0, 0)][DBLP]
    ISAAC, 1994, pp:378-386 [Conf]
  162. Vigyan Singhal, Robert K. Brayton, Carl Pixley
    Power-Up Delay for Retiming Digital Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:566-569 [Conf]
  163. Robert K. Brayton, M. Gao, Jie-Hong Roland Jiang, Yunjian Jiang, Yinghua Li, Alan Mishchenko, Subarnarekha Sinha, Tiziano Villa
    Optimization of Multi-Valued Multi-Level Networks. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:168-0 [Conf]
  164. Fan Mo, Robert K. Brayton
    Fishbone: a block-level placement and routing scheme. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:204-209 [Conf]
  165. Zhongcheng Li, Robert K. Brayton, Yinghua Min
    Efficient Identification of Non-Robustly Untestable Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:992-997 [Conf]
  166. Jie-Hong Roland Jiang, Robert K. Brayton
    On the Verification of Sequential Equivalence. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:307-314 [Conf]
  167. Yunjian Jiang, Robert K. Brayton
    Don't Care Computation in Minimizing Extended Finite State Machines with Presburger Arithmetic. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:327-332 [Conf]
  168. Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton
    Reducing Multi-Valued Algebraic Operations to Binary. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:339-344 [Conf]
  169. Alan Mishchenko, Robert K. Brayton
    A Boolean Paradigm in Multi-Valued Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:173-177 [Conf]
  170. Alan Mishchenko, Robert K. Brayton
    Simplification of Non-Deterministic Multi-Valued Networks. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:333-338 [Conf]
  171. Fan Mo, Robert K. Brayton
    Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:7-12 [Conf]
  172. Subarnarekha Sinha, Alan Mishchenko, Robert K. Brayton
    Topologically Constrained Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:13-20 [Conf]
  173. Nina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alexandre Petrenko, Alberto L. Sangiovanni-Vincentelli
    Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:45-50 [Conf]
  174. Sriram C. Krishnan, Anuj Puri, Robert K. Brayton
    Structural Complexity of Omega-Automata. [Citation Graph (0, 0)][DBLP]
    STACS, 1995, pp:143-156 [Conf]
  175. Ellen Sentovich, Robert K. Brayton
    Preserving Don't Care Conditions During Retiming. [Citation Graph (0, 0)][DBLP]
    VLSI, 1991, pp:461-470 [Conf]
  176. Robert K. Brayton, Sunil P. Khatri
    Multi-Valued Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:196-105 [Conf]
  177. Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Sequential Multi-Valued Network Simplification using Redundancy Removal. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:206-211 [Conf]
  178. Patrick C. McGeer, Jagesh V. Sanghavi, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Minimization of Logic Functions Using Essential Signature Sets. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:323-328 [Conf]
  179. Amit Narayan, Sunil P. Khatri, Jawahar Jain, Masahiro Fujita, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    A study of composition schemes for mixed apply/compose based construction of ROBDDs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:249-253 [Conf]
  180. Alexander Saldanha, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Functional clock schedule optimization. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:93-98 [Conf]
  181. Gitanjali Swamy, Stephen A. Edwards, Robert K. Brayton
    Efficient Verification and Synthesis using Design Commonalities. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:542-551 [Conf]
  182. Rajeev Alur, Robert K. Brayton, Thomas A. Henzinger, Shaz Qadeer, Sriram K. Rajamani
    Partial-Order Reduction in Symbolic State-Space Exploration. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2001, v:18, n:2, pp:97-116 [Journal]
  183. Adnan Aziz, Thomas R. Shiple, Vigyan Singhal, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Formula-Dependent Equivalence for Compositional CTL Model Checking. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2002, v:21, n:2, pp:193-224 [Journal]
  184. Ramin Hojati, Robert K. Brayton
    An Environment for Formal Verification Based on Symbolic Computations. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1995, v:6, n:2, pp:191-216 [Journal]
  185. Stefano Quer, Gianpiero Cabodi, Paolo Camurati, Luciano Lavagno, Ellen Sentovich, Robert K. Brayton
    Verification of Similar FSMs by Mixing Incremental Re-encoding, Reachability Analysis, and Combinational Checks. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2000, v:17, n:2, pp:107-134 [Journal]
  186. Hervé J. Touati, Robert K. Brayton, Robert P. Kurshan
    Testing Language Containment for omega-Automata Using BDD's [Citation Graph (0, 0)][DBLP]
    Inf. Comput., 1995, v:118, n:1, pp:101-109 [Journal]
  187. Ralph H. J. M. Otten, Robert K. Brayton
    Performance planning. [Citation Graph (0, 0)][DBLP]
    Integration, 2000, v:29, n:1, pp:1-24 [Journal]
  188. Abdallah Tabbara, Bassam Tabbara, Robert K. Brayton, A. Richard Newton
    Integration of retiming with architectural floorplanning. [Citation Graph (0, 0)][DBLP]
    Integration, 2000, v:29, n:1, pp:25-43 [Journal]
  189. Abdul A. Malik, Robert K. Brayton, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
    Two-Level Minimization of Multivalued Functions with Large Offsets. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:11, pp:1325-1342 [Journal]
  190. Adnan Aziz, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Sequential synthesis using S1S. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:10, pp:1149-1162 [Journal]
  191. Karen A. Bartlett, Robert K. Brayton, Gary D. Hachtel, Reily M. Jacoby, Christopher R. Morrison, Richard L. Rudell, Alberto L. Sangiovanni-Vincentelli, Albert R. Wang
    Multi-level logic minimization using implicit don't cares. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:6, pp:723-740 [Journal]
  192. Robert K. Brayton, Richard L. Rudell, Alberto L. Sangiovanni-Vincentelli, Albert R. Wang
    MIS: A Multiple-Level Logic Optimization System. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:6, pp:1062-1081 [Journal]
  193. Evguenii I. Goldberg, Luca P. Carloni, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Negative thinking in branch-and-bound: the case of unate covering. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:3, pp:281-294 [Journal]
  194. Evguenii I. Goldberg, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Theory and algorithms for face hypercube embedding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:6, pp:472-488 [Journal]
  195. Jie-Hong Roland Jiang, Robert K. Brayton
    On the verification of sequential equivalence. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:686-697 [Journal]
  196. Sunil P. Khatri, Subarnarekha Sinha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    SPFD-based wire removal in standard-cell and network-of-PLA circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:1020-1030 [Journal]
  197. Timothy Kam, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Implicit computation of compatible sets for state minimization of ISFSMs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:7, pp:657-676 [Journal]
  198. Timothy Kam, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Theory and algorithms for state minimization of nondeterministic FSMs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:11, pp:1311-1322 [Journal]
  199. William K. C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Valid clock frequencies and their computation in wavepipelined circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:7, pp:791-807 [Journal]
  200. William K. Lam, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Delay fault coverage, test set size, and performance trade-offs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:1, pp:32-44 [Journal]
  201. Luciano Lavagno, Cho W. Moon, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    An efficient heuristic procedure for solving the state assignment problem for event-based specifications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:1, pp:45-60 [Journal]
  202. Abdul A. Malik, Robert K. Brayton, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
    Reduced offsets for minimization of binary-valued functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:4, pp:413-426 [Journal]
  203. Sharad Malik, Luciano Lavagno, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Symbolic minimization of multilevel logic and the input encoding problem. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:7, pp:825-843 [Journal]
  204. Sharad Malik, Ellen M. Sentovich, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Retiming and resynthesis: optimizing sequential networks with combinational techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:1, pp:74-84 [Journal]
  205. Sharad Malik, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Performance optimization of pipelined logic circuits using peripheral retiming and resynthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:5, pp:568-578 [Journal]
  206. Fan Mo, Robert K. Brayton
    PLA-based regular structures and their synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:723-729 [Journal]
  207. Alan Mishchenko, Jin S. Zhang, Subarnarekha Sinha, Jerry R. Burch, Robert K. Brayton, Malgorzata Chrzanowska-Jeske
    Using simulation and satisfiability to compute flexibilities in Boolean networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:743-755 [Journal]
  208. Giovanni De Micheli, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Optimal State Assignment for Finite State Machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:3, pp:269-285 [Journal]
  209. Giovanni De Micheli, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Correction to "Optimal State Assignment for Finite State Machines". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:1, pp:239-239 [Journal]
  210. Alan Mishchenko, Robert K. Brayton
    A theory of nondeterministic networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:977-999 [Journal]
  211. Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Circuit structure relations to redundancy and delay. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:7, pp:875-883 [Journal]
  212. Alexander Saldanha, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Satisfaction of input and output encoding constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:5, pp:589-602 [Journal]
  213. Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K. Brayton
    Theory of safe replacements for sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:2, pp:249-265 [Journal]
  214. Paul R. Stephan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Combinational test generation using satisfiability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:9, pp:1167-1176 [Journal]
  215. Hervé J. Touati, Robert K. Brayton
    Computing the initial states of retimed circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:1, pp:157-162 [Journal]
  216. Tiziano Villa, Timothy Kam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Explicit and implicit algorithms for binate covering problems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:7, pp:677-691 [Journal]
  217. Tiziano Villa, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Symbolic two-level minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:7, pp:692-708 [Journal]
  218. Yosinori Watanabe, Robert K. Brayton
    Heuristic minimization of multiple-valued relations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1458-1472 [Journal]
  219. Yosinori Watanabe, Lisa Guerra, Robert K. Brayton
    Permissible functions for multioutput components in combinational logic optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:7, pp:732-744 [Journal]
  220. Adnan Aziz, Kumud Sanwal, Vigyan Singhal, Robert K. Brayton
    Model-checking continous-time Markov chains. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Comput. Log., 2000, v:1, n:1, pp:162-170 [Journal]
  221. Vigyan Singhal, Carl Pixley, Adnan Aziz, Shaz Qadeer, Robert K. Brayton
    Sequential optimization in the absence of global reset. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:2, pp:222-251 [Journal]
  222. Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Andreas Kuehlmann
    On Resolution Proofs for Combinational Equivalence. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:600-605 [Conf]
  223. Fan Mo, Robert K. Brayton
    Semi-detailed bus routing with variation reduction. [Citation Graph (0, 0)][DBLP]
    ISPD, 2007, pp:143-150 [Conf]
  224. Alan Mishchenko, Robert K. Brayton
    SAT-Based Complete Don't-Care Computation for Network Optimization [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  225. Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Tiziano Villa, Nina Yevtushenko
    Efficient Solution of Language Equations Using Partitioned Representations [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  226. Patrick C. McGeer, Jagesh V. Sanghavi, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    ESPRESSO-SIGNATURE: a new exact minimizer for logic functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:4, pp:432-440 [Journal]

  227. Automating Logic Rectification by Approximate SPFDs. [Citation Graph (, )][DBLP]


  228. ABC: An Academic Industrial-Strength Verification Tool. [Citation Graph (, )][DBLP]


  229. Scalable min-register retiming under timing and initializability constraints. [Citation Graph (, )][DBLP]


  230. Merging nodes under sequential observability. [Citation Graph (, )][DBLP]


  231. Speculative reduction-based scalable redundancy identification. [Citation Graph (, )][DBLP]


  232. Sequential logic rectifications with approximate SPFDs. [Citation Graph (, )][DBLP]


  233. Exploiting power-up delay for sequential optimization. [Citation Graph (, )][DBLP]


  234. Automated Extraction of Inductive Invariants to Aid Model Checking. [Citation Graph (, )][DBLP]


  235. Recording Synthesis History for Sequential Verification. [Citation Graph (, )][DBLP]


  236. Invariant-Strengthened Elimination of Dependent State Elements. [Citation Graph (, )][DBLP]


  237. Fast Minimum-Register Retiming via Binary Maximum-Flow. [Citation Graph (, )][DBLP]


  238. Global delay optimization using structural choices. [Citation Graph (, )][DBLP]


  239. Scalable don't-care-based logic optimization and resynthesis. [Citation Graph (, )][DBLP]


  240. SmartOpt: an industrial strength framework for logic synthesis. [Citation Graph (, )][DBLP]


  241. A simultaneous bus orientation and bused pin flipping algorithm. [Citation Graph (, )][DBLP]


  242. Combinational and sequential mapping with priority cuts. [Citation Graph (, )][DBLP]


  243. Boolean factoring and decomposition of logic networks. [Citation Graph (, )][DBLP]


  244. Placement based multiplier rewiring for cell-based designs. [Citation Graph (, )][DBLP]


  245. Scalable and scalably-verifiable sequential synthesis. [Citation Graph (, )][DBLP]


  246. NSF Workshop on EDA: Past, Present, and Future (Part 1). [Citation Graph (, )][DBLP]


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