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## Search the dblp DataBase
Emmanuelle Encrenaz:
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## Publications of Author- Vincent Beaudenon, Emmanuelle Encrenaz, Jean Lou Desbarbieux
**Design Validation of ZCSP with SPIN.**[Citation Graph (0, 0)][DBLP] ACSD, 2003, pp:102-110 [Conf] - Jean-Michel Couvreur, Emmanuelle Encrenaz, Emmanuel Paviot-Adet, Denis Poitrenaud, Pierre-André Wacrenier
**Data Decision Diagrams for Petri Net Analysis.**[Citation Graph (0, 0)][DBLP] ICATPN, 2002, pp:101-120 [Conf] - Emmanuelle Encrenaz
**A Symbolic Relation for a Subset of VHDL'87 Descriptions and its Application to Symbolic Model Checking.**[Citation Graph (0, 0)][DBLP] CHARME, 1995, pp:328-342 [Conf] - Cédric Roux, Emmanuelle Encrenaz
**CTL May Be Ambiguous When Model Checking Moore Machines.**[Citation Graph (0, 0)][DBLP] CHARME, 2003, pp:164-169 [Conf] - Rajesh K. Bawa, Emmanuelle Encrenaz
**A Tool for Translation of VHDL Descriptions into a Formal Model and its Application to Formal Verification and Synthesis.**[Citation Graph (0, 0)][DBLP] FTRTFT, 1996, pp:471-474 [Conf] - Cécile Braunstein, Emmanuelle Encrenaz
**Formalizing the Incremental Design and Verification Process of a Pipelined Protocol Converter.**[Citation Graph (0, 0)][DBLP] IEEE International Workshop on Rapid System Prototyping, 2006, pp:103-109 [Conf] - Cécile Braunstein, Emmanuelle Encrenaz
**CTL-Property Transformations Along an Incremental Design Process.**[Citation Graph (0, 0)][DBLP] Electr. Notes Theor. Comput. Sci., 2005, v:128, n:6, pp:263-278 [Journal] - Cécile Braunstein, Emmanuelle Encrenaz
**Using CTL formulae as component abstraction in a design and verification flow.**[Citation Graph (0, 0)][DBLP] ACSD, 2007, pp:80-89 [Conf] - Fahim Rahim-Sarwary, Emmanuelle Encrenaz, Michel Minoux, Rajesh K. Bawa
**Modular model checking of VLSI designs described in VHDL.**[Citation Graph (0, 0)][DBLP] Computers and Their Applications, 1998, pp:368-371 [Conf] - Cécile Braunstein, Emmanuelle Encrenaz
**CTL-property Transformations along an Incremental Design Process.**[Citation Graph (0, 0)][DBLP] STTT, 2007, v:9, n:1, pp:77-88 [Journal] **Complementary Formal Approaches for Dependability Analysis.**[Citation Graph (, )][DBLP]**A Polynomial Algorithm to Prove Deadlock-Freeness of Wormhole Networks.**[Citation Graph (, )][DBLP]**Time Separation of Events: An Inverse Method.**[Citation Graph (, )][DBLP]**An Inverse Method for Parametric Timed Automata.**[Citation Graph (, )][DBLP]**Automatic Verification of Counter Systems With Ranking Function.**[Citation Graph (, )][DBLP]
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