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## Search the dblp DataBase
Satoshi Yamane:
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## Publications of Author- Kazuhiro Nakamura, Satoshi Yamane
**Formal Verification of Real-Time Software by Symbolic Model-Checker.**[Citation Graph (0, 0)][DBLP] ACSD, 1998, pp:99-108 [Conf] - Satoshi Yamane
**Formal Specification and Verification Method of Concurrent and Distributed Systems by Restricted Timed Automata.**[Citation Graph (0, 0)][DBLP] ARTS, 1997, pp:169-183 [Conf] - Satoshi Yamane
**Probabilistic Timed Simulation Verification and Its Application to Stepwise Refinement of Real-Time Systems.**[Citation Graph (0, 0)][DBLP] ASIAN, 2003, pp:276-290 [Conf] - Satoshi Yamane
**Deductive Schedulability Verification Methodology of Real-Time Software using both Refinement Verification and Hybrid Automata.**[Citation Graph (0, 0)][DBLP] COMPSAC, 2003, pp:527-533 [Conf] - Satoshi Yamane
**Timed Weak Simulation Verification and Its Application to Stepwise Refinement of Real-Time Software.**[Citation Graph (0, 0)][DBLP] EUC, 2005, pp:381-394 [Conf] - Satoshi Yamane
**Automata-Theoretic Performance Analysis Method of Soft Real-Time Systems.**[Citation Graph (0, 0)][DBLP] EUC Workshops, 2005, pp:1211-1224 [Conf] - Satoshi Yamane, Takashi Kanatani
**Deductive Probabilistic Verification Methods for Embedded and Ubiquitous Computing.**[Citation Graph (0, 0)][DBLP] EUC, 2004, pp:183-195 [Conf] - Satoshi Yamane
**A Practical Hierarchical Design by Timed Simulation Relations for Real-Time Systems.**[Citation Graph (0, 0)][DBLP] FM-Trends, 1998, pp:151-167 [Conf] - Satoshi Yamane
**Formal Timing Verification Techniques for Distributed System .**[Citation Graph (0, 0)][DBLP] FTDCS, 1995, pp:454-460 [Conf] - Satoshi Yamane
**Deductive Verification of Probabilistic Real-Time Systems.**[Citation Graph (0, 0)][DBLP] ICDCS Workshops, 2004, pp:622-627 [Conf] - Satoshi Yamane
**Deductive Probabilistic Verification Methods of Safety, Liveness and Nonzenoness for Distributed Real-Time Systems.**[Citation Graph (0, 0)][DBLP] ICESS, 2005, pp:332-345 [Conf] - Yosuke Mutsuda, Takaaki Kato, Satoshi Yamane
**Specification and Verification Techniques of Embedded Systems Using Probabilistic Linear Hybrid Automata.**[Citation Graph (0, 0)][DBLP] ICESS, 2005, pp:346-360 [Conf] - Satoshi Yamane
**Real-Time Object-Oriented Method.**[Citation Graph (0, 0)][DBLP] OOIS, 1995, pp:287-302 [Conf] - Kazuhiko Eguchi, Junya Suzuki, Satoshi Yamane, Kenji Oshima
**An Application of Genetic Algorithms to Floorplanning of VLSI.**[Citation Graph (0, 0)][DBLP] Rough Sets and Current Trends in Computing, 1998, pp:263-270 [Conf] - Kazuhiko Eguchi, Satoshi Yamane, Hideo Sugi, Kenji Oshima
**Sensing of Arc Length and Wire Extension Using Neural Network in Robotic Welding.**[Citation Graph (0, 0)][DBLP] Rough Sets and Current Trends in Computing, 1998, pp:163-170 [Conf] - Satoshi Yamane, Kazuhiro Okada, Kenji Shinoda, Kenji Oshima
**Traffic Signal Control Using Multi-layered Fuzzy Control.**[Citation Graph (0, 0)][DBLP] Rough Sets and Current Trends in Computing, 1998, pp:171-177 [Conf] - Y. Tachi, Satoshi Yamane
**Real-Time Symbolic Model Checking for Hard Real-Time Systems.**[Citation Graph (0, 0)][DBLP] RTCSA, 1999, pp:496-0 [Conf] - Satoshi Yamane
**Verification system for real-time specification based on extended real-time logic.**[Citation Graph (0, 0)][DBLP] RTCSA, 1995, pp:192-196 [Conf] - Satoshi Yamane
**Hierarchical Design Method for Real-Time Distributed Systems.**[Citation Graph (0, 0)][DBLP] RTCSA, 1998, pp:189-0 [Conf] - Satoshi Yamane, Kazuhiro Nakamura
**Symbolic Model-Checking Method Based on Approximations and Binary Decision Diagrams for Real-Time Systems.**[Citation Graph (0, 0)][DBLP] TACS, 1997, pp:562-582 [Conf] - Satoshi Yamane
**Formal Probabilistic Refinement Verification of Embedded Real-Time Systems.**[Citation Graph (0, 0)][DBLP] WSTFEUS, 2003, pp:79-82 [Conf] - Satoshi Yamane
**A method for the specification and verification of distributed systems by a timed automaton.**[Citation Graph (0, 0)][DBLP] Systems and Computers in Japan, 1997, v:28, n:2, pp:11-20 [Journal] - Satoshi Yamane, Kazuhiro Nakamura
**Development and evaluation of symbolic model checker based on approximation for real-time systems.**[Citation Graph (0, 0)][DBLP] Systems and Computers in Japan, 2004, v:35, n:10, pp:83-101 [Journal] - Satoshi Yamane
**Theory and Practice of Probabilistic Timed Game for Embedded Systems.**[Citation Graph (0, 0)][DBLP] ICESS, 2007, pp:109-120 [Conf]
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