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Jerry R. Burch: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jerry R. Burch, Edmund M. Clarke, Kenneth L. McMillan, David L. Dill, L. J. Hwang
    Symbolic Model Checking: 10^20 States and Beyond [Citation Graph (1, 0)][DBLP]
    Inf. Comput., 1992, v:98, n:2, pp:142-170 [Journal]
  2. Jerry R. Burch, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli
    Overcoming Heterophobia: Modeling Concurrency in Heterogeneous Systems. [Citation Graph (0, 0)][DBLP]
    ACSD, 2001, pp:13-0 [Conf]
  3. Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch
    Detecting support-reducing bound sets using two-cofactor symmetries. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:266-271 [Conf]
  4. Jerry R. Burch
    Combining CTL, Trace Theory and Timing Models. [Citation Graph (0, 0)][DBLP]
    Automatic Verification Methods for Finite State Systems, 1989, pp:334-348 [Conf]
  5. Jerry R. Burch
    Verifying Liveness Properties by Verifying Safety Properties. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:224-232 [Conf]
  6. Jerry R. Burch, David L. Dill
    Automatic verification of Pipelined Microprocessor Control. [Citation Graph (0, 0)][DBLP]
    CAV, 1994, pp:68-80 [Conf]
  7. Jerry R. Burch
    Using BDDs to Verify Multipliers. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:408-412 [Conf]
  8. Jerry R. Burch
    Techniques for Verifying Superscalar Microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:552-557 [Conf]
  9. Jerry R. Burch, Edmund M. Clarke, David E. Long
    Representing Circuits More Efficiently in Symbolic Model Checking. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:403-407 [Conf]
  10. Jerry R. Burch, Edmund M. Clarke, Kenneth L. McMillan, David L. Dill
    Sequential Circuit Verification Using Symbolic Model Checking. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:46-51 [Conf]
  11. Youpyo Hong, Peter A. Beerel, Jerry R. Burch, Kenneth L. McMillan
    Safe BDD Minimization Using Don't Cares. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:208-213 [Conf]
  12. Jerry R. Burch, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli
    Using Multiple Levels of Abstractions in Embedded Software Design. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2001, pp:324-343 [Conf]
  13. Roberto Passerone, Jerry R. Burch, Alberto L. Sangiovanni-Vincentelli
    Conservative approximations for heterogeneous design. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2004, pp:155-164 [Conf]
  14. Phillip J. Windley, Jerry R. Burch
    Mechanically Checking a Lemma Used in an Automatic Verification Tool. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1996, pp:362-376 [Conf]
  15. Peter A. Beerel, Jerry R. Burch, Teresa H. Y. Meng
    Efficient verification of determinate speed-independent circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:261-267 [Conf]
  16. Jerry R. Burch, David L. Dill, Elizabeth Wolf, Giovanni De Micheli
    Modeling hierarchical combinational circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:612-617 [Conf]
  17. Jerry R. Burch, David E. Long
    Efficient Boolean function matching. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:408-411 [Conf]
  18. Jerry R. Burch, Vigyan Singhal
    Robust latch mapping for combinational equivalence checking. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:563-569 [Conf]
  19. Jerry R. Burch, Vigyan Singhal
    Tight integration of combinational verification methods. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:570-576 [Conf]
  20. Robert B. Jones, David L. Dill, Jerry R. Burch
    Efficient validity checking for processor verification. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:2-6 [Conf]
  21. Jerry R. Burch
    Delay Models for Verifying Speed-Dependent Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:270-274 [Conf]
  22. Jerry R. Burch, Edmund M. Clarke, Kenneth L. McMillan, David L. Dill, L. J. Hwang
    Symbolic Model Checking: 10^20 States and Beyond [Citation Graph (0, 0)][DBLP]
    LICS, 1990, pp:428-439 [Conf]
  23. Jerry R. Burch, Edmund M. Clarke, David E. Long
    Symbolic Model Checking with Partitioned Transistion Relations. [Citation Graph (0, 0)][DBLP]
    VLSI, 1991, pp:49-58 [Conf]
  24. Peter A. Beerel, Jerry R. Burch, Teresa H. Y. Meng
    Checking Combinational Equivalence of Speed-Independent Circuits. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1998, v:13, n:1, pp:37-85 [Journal]
  25. Alain J. Martin, Jerry R. Burch
    Fair Mutual Exclusion with Unfair P and V Operations. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1985, v:21, n:2, pp:97-100 [Journal]
  26. Jerry R. Burch, Edmund M. Clarke, David E. Long, Kenneth L. McMillan, David L. Dill
    Symbolic model checking for sequential circuit verification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:4, pp:401-424 [Journal]
  27. Youpyo Hong, Peter A. Beerel, Jerry R. Burch, Kenneth L. McMillan
    Sibling-substitution-based BDD minimization using don't cares. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:1, pp:44-55 [Journal]
  28. Alan Mishchenko, Jin S. Zhang, Subarnarekha Sinha, Jerry R. Burch, Robert K. Brayton, Malgorzata Chrzanowska-Jeske
    Using simulation and satisfiability to compute flexibilities in Boolean networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:743-755 [Journal]
  29. Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch
    Linear cofactor relationships in Boolean functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1011-1023 [Journal]
  30. Alfred Koelbl, Jerry R. Burch, Carl Pixley
    Memory Modeling in ESL-RTL Equivalence Checking. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:205-209 [Conf]
  31. Roberto Passerone, Jerry R. Burch, Alberto L. Sangiovanni-Vincentelli
    Refinement preserving approximations for the design and verification of heterogeneous systems. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2007, v:31, n:1, pp:1-33 [Journal]

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