The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Oscar Garnica: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Oscar Garnica, Juan Lanchares, Román Hermida
    Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation. [Citation Graph (0, 0)][DBLP]
    ACSD, 2001, pp:167-178 [Conf]
  2. Oscar Garnica, Juan Lanchares, Román Hermida
    A pseudo delay-insensitive timing model to synthesizing low-power asynchronous circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:810- [Conf]
  3. Guadalupe Miñana, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar
    A Power-Aware Technique for Functional Units in High-Performance Processors. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:456-459 [Conf]
  4. José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López
    Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:423-432 [Conf]
  5. José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López
    Sim-async: An Architectural Simulator for Asynchronous Processor Modeling Using Distribution Functions. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2006, pp:495-505 [Conf]
  6. José Ignacio Hidalgo, Francisco Fernández de Vega, Juan Lanchares, Juan Manuel Sánchez-Pérez, Román Hermida, Marco Tomassini, Ranieri Baraglia, Raffaele Perego, Oscar Garnica
    Multi-FPGA Systems Synthesis by Means of Evolutionary Computation. [Citation Graph (0, 0)][DBLP]
    GECCO, 2003, pp:2109-2120 [Conf]
  7. Oscar Garnica, Juan Lanchares, Román Hermida
    A New Methodology to Design Low-Power Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:108-117 [Conf]
  8. Guadalupe Miñana, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar
    Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:40-48 [Conf]
  9. Guadalupe Miñana, José Ignacio Hidalgo, Oscar Garnica, Juan Lanchares, José Manuel Colmenar, Sonia López
    A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:514-523 [Conf]
  10. Sonia López, Oscar Garnica, José Manuel Colmenar
    Enhancing GALS Processor Performance Using Data Classification Based on Data Latency. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:623-632 [Conf]
  11. Sonia López, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, Román Hermida
    Power-Consumption RRRRreduction in Asynchronous Circuits Using Delay Path Unequalization. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:151-160 [Conf]
  12. José Manuel Colmenar, Oscar Garnica, Sonia López, José Ignacio Hidalgo, Juan Lanchares, Román Hermida
    Empirical Characterization of the Latency of Long Asynchronous Pipelines with Data-Dependent Module Delays. [Citation Graph (0, 0)][DBLP]
    PDP, 2004, pp:112-119 [Conf]
  13. José Ignacio Hidalgo, Manuel Prieto, Juan Lanchares, Ranieri Baraglia, Francisco Tirado, Oscar Garnica
    Hybrid Parallelization of a Compact Genetic Algorithm. [Citation Graph (0, 0)][DBLP]
    PDP, 2003, pp:449-455 [Conf]
  14. Oscar Garnica, Juan Lanchares, Román Hermida
    Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation. [Citation Graph (0, 0)][DBLP]
    Fundam. Inform., 2002, v:50, n:2, pp:155-174 [Journal]
  15. Sonia López, Steve Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares
    Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2007, pp:136-150 [Conf]

  16. Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors. [Citation Graph (, )][DBLP]


  17. Solving discrete deceptive problems with EMMRS. [Citation Graph (, )][DBLP]


  18. Mixed heuristic and mathematical programming using reference points for dynamic data types optimization in multimedia embedded systems. [Citation Graph (, )][DBLP]


  19. Improving SMT performance: an application of genetic algorithms to configure resizable caches. [Citation Graph (, )][DBLP]


  20. Improving reliability of embedded systems through dynamic memory manager optimization using grammatical evolution. [Citation Graph (, )][DBLP]


  21. Modelling Asynchronous Systems using Probability Distribution Functions. [Citation Graph (, )][DBLP]


Search in 0.005secs, Finished in 0.006secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002