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Román Hermida: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Oscar Garnica, Juan Lanchares, Román Hermida
    Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation. [Citation Graph (0, 0)][DBLP]
    ACSD, 2001, pp:167-178 [Conf]
  2. Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida
    Arrival time aware scheduling to minimize clock cycle length. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1018-1021 [Conf]
  3. F. Rivera, Marcos Sanchez-Elez, Milagros Fernández, Román Hermida, Nader Bagherzadeh
    Efficient mapping of hierarchical trees on coarse-grain reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:30-35 [Conf]
  4. María C. Molina, José M. Mendías, Román Hermida
    High-level synthesis of multiple-precision circuitsindependent of data-objects length. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:612-615 [Conf]
  5. Oscar Garnica, Juan Lanchares, Román Hermida
    A pseudo delay-insensitive timing model to synthesizing low-power asynchronous circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:810- [Conf]
  6. Nicolas Genko, David Atienza, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida, Francky Catthoor
    A Complete Network-On-Chip Emulation Framework. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:246-251 [Conf]
  7. Rafael Maestre, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh, Román Hermida, Milagros Fernández
    Kernel Scheduling in Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:90-96 [Conf]
  8. J. A. Maestro, Daniel Mozos, Román Hermida
    The Heterogeneous Structure Problem in Hardware/Software Codesign: A Macroscopic Approach. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:766-767 [Conf]
  9. José M. Mendías, Román Hermida
    Correct High-Level Synthesis: a Formal Perspective. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:977-978 [Conf]
  10. María C. Molina, José M. Mendías, Román Hermida
    Multiple-Precision Circuits Allocation Independent of Data-Objects Length. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:909-915 [Conf]
  11. María C. Molina, José M. Mendías, Román Hermida
    High-Level Allocation to Minimize Internal Hardware Wastage. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10264-10269 [Conf]
  12. María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida
    Behavioural Bitwise Scheduling Based on Computational Effort Balancing. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:684-685 [Conf]
  13. Olga Peñalba, José M. Mendías, Román Hermida
    Maximizing Conditonal Reuse by Pre-Synthesis Transformations. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1097- [Conf]
  14. Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida
    Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1252-1257 [Conf]
  15. Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida
    Pre-synthesis optimization of multiplications to improve circuit performance. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1306-1311 [Conf]
  16. Marcos Sanchez-Elez, Milagros Fernández, Manuel L. Anido, Haitao Du, Nader Bagherzadeh, Román Hermida
    Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10036-10043 [Conf]
  17. Marcos Sanchez-Elez, Milagros Fernández, Rafael Maestre, Fadi J. Kurdahi, Román Hermida, Nader Bagherzadeh
    A Complete Data Scheduler for Multi-Context Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:547-552 [Conf]
  18. Juan de Vicente, Juan Lanchares, Román Hermida
    FPGA Placement by Thermodynamic Combinatorial Optimization. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:54-60 [Conf]
  19. José Ignacio Hidalgo, Juan Lanchares, Aitor Ibarra, Román Hermida
    A Hybrid Evolutionary Algorithm for Multi-FPGA Systems Design. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:60-69 [Conf]
  20. Aitor Ibarra, José M. Mendías, Juan Lanchares, José Ignacio Hidalgo, Román Hermida
    Optimization of Equational Specifications Using Genetic Techniques. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:252-258 [Conf]
  21. Olga Peñalba, José M. Mendías, Román Hermida
    Source Code Transformation to Improve Conditional Hardware Reuse. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:324-331 [Conf]
  22. José M. Mendías, Román Hermida, María C. Molina, Olga Peñalba
    Efficient Verification of Scheduling, Allocation and Binding in High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:308-315 [Conf]
  23. María C. Molina, José M. Mendías, Román Hermida
    Bit-Level Allocation of Multiple-Precision Specifications. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:385-392 [Conf]
  24. Aitor Ibarra, Juan Lanchares, Jose Manuel Mendias, José Ignacio Hidalgo, Román Hermida
    Transformation of Equational Specification by Means of Genetic Programming. [Citation Graph (0, 0)][DBLP]
    EuroGP, 2002, pp:248-257 [Conf]
  25. José Ignacio Hidalgo, Juan Lanchares, Román Hermida
    Partitioning and Placement for Multi-FPGA Systems Using Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:1204-1211 [Conf]
  26. Olga Peñalba, José M. Mendías, Román Hermida
    A Unified Algorithm for Mutual Exclusiveness Identification. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1504-1510 [Conf]
  27. Juan de Vicente, Juan Lanchares, Román Hermida
    RSR: A New Rectilinear Steiner Minimum Tree Approximation for FPGA Placement and Global Routing. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10192-10195 [Conf]
  28. Rafael Maestre, Milagros Fernández, Román Hermida, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh
    Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:297-298 [Conf]
  29. Juan de Vicente, Juan Lanchares, Román Hermida
    Placement Optimization Based on Global Routing Updating for System Partitioning onto Multi-FPGA Mesh Topologies. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:91-100 [Conf]
  30. José Ignacio Hidalgo, Francisco Fernández de Vega, Juan Lanchares, Juan Manuel Sánchez-Pérez, Román Hermida, Marco Tomassini, Ranieri Baraglia, Raffaele Perego, Oscar Garnica
    Multi-FPGA Systems Synthesis by Means of Evolutionary Computation. [Citation Graph (0, 0)][DBLP]
    GECCO, 2003, pp:2109-2120 [Conf]
  31. María C. Molina, José M. Mendías, Román Hermida
    Bit-level scheduling of heterogeneous behavioural specifications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:602-608 [Conf]
  32. Rafael Ruiz-Sautua, María C. Molina, Jose Manuel Mendias, Román Hermida
    Performance-driven read-after-write dependencies softening in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:7-12 [Conf]
  33. Rafael Maestre, Milagros Fernández, Román Hermida, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh
    Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:575-576 [Conf]
  34. F. Rivera, Marcos Sanchez-Elez, Milagros Fernández, Román Hermida, Nader Bagherzadeh
    Low Power Data Prefetch for 3D Image Applications on Coarse-Grain Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  35. Nicolas Genko, David Atienza, Giovanni De Micheli, Luca Benini, Jose Manuel Mendias, Román Hermida, Francky Catthoor
    A novel approach for network on chip emulation. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2365-2368 [Conf]
  36. Rafael Maestre, Milagros Fernández, Román Hermida, Nader Bagherzadeh
    A Framework for Scheduling and Context Allocation in Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    ISSS, 1999, pp:134-140 [Conf]
  37. Marcos Sanchez-Elez, Milagros Fernández, Román Hermida, Rafael Maestre, Fadi J. Kurdahi, Nader Bagherzadeh
    A data scheduler for multi-context reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:177-182 [Conf]
  38. María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida
    Behavioural Scheduling to Balance the Bit-Level Computational Effort. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:99-104 [Conf]
  39. J. B. Pérez-Ramas, David Atienza, M. Peón, Ivan Magan, Jose Manuel Mendias, Román Hermida
    Versatile FPGA-Based Functional Validation Framework for Networks-on-Chip Interconnections Designs. [Citation Graph (0, 0)][DBLP]
    PARCO, 2005, pp:769-776 [Conf]
  40. Oscar Garnica, Juan Lanchares, Román Hermida
    A New Methodology to Design Low-Power Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:108-117 [Conf]
  41. María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida
    Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:617-627 [Conf]
  42. Sonia López, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, Román Hermida
    Power-Consumption RRRRreduction in Asynchronous Circuits Using Delay Path Unequalization. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:151-160 [Conf]
  43. José Manuel Colmenar, Oscar Garnica, Sonia López, José Ignacio Hidalgo, Juan Lanchares, Román Hermida
    Empirical Characterization of the Latency of Long Asynchronous Pipelines with Data-Dependent Module Delays. [Citation Graph (0, 0)][DBLP]
    PDP, 2004, pp:112-119 [Conf]
  44. Juan de Vicente, Juan Lanchares, Román Hermida
    Adaptive FPGA Placement by Natural Optimization. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:188-193 [Conf]
  45. José M. Mendías, Román Hermida, Milagros Fernández
    Formal Techniques for Hardware Allocation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:161-165 [Conf]
  46. Oscar Garnica, Juan Lanchares, Román Hermida
    Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation. [Citation Graph (0, 0)][DBLP]
    Fundam. Inform., 2002, v:50, n:2, pp:155-174 [Journal]
  47. José M. Mendías, Román Hermida, Olga Peñalba
    A study about the efficiency of formal high-level synthesis applied to verification. [Citation Graph (0, 0)][DBLP]
    Integration, 2002, v:31, n:2, pp:101-131 [Journal]
  48. R. Moreno, Román Hermida, Milagros Fernández, Hortensia Mecha
    A unified approach for scheduling and allocation. [Citation Graph (0, 0)][DBLP]
    Integration, 1997, v:23, n:1, pp:1-35 [Journal]
  49. María C. Molina, José M. Mendías, Román Hermida
    Allocation of multiple precision behaviors for maximal bit level reuse of hardware resources. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2003, v:49, n:12-15, pp:505-519 [Journal]
  50. María C. Molina, Rafael Ruiz-Sautua, Jose Manuel Mendias, Román Hermida
    Bitwise scheduling to balance the computational cost of behavioral specifications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:31-46 [Journal]
  51. R. Moreno, Román Hermida, Milagros Fernández
    Register estimation in unscheduled dataflow graphs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1996, v:1, n:3, pp:396-403 [Journal]
  52. Juan de Vicente, Juan Lanchares, Román Hermida
    Annealing placement by thermodynamic combinatorial optimization. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2004, v:9, n:3, pp:310-332 [Journal]
  53. María C. Molina, Rafael Ruiz-Sautua, Jose Manuel Mendias, Román Hermida
    Area optimization of multi-cycle operators in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:449-454 [Conf]
  54. F. Rivera, Marcos Sanchez-Elez, Milagros Fernández, Román Hermida, Nader Bagherzadeh
    Configuration Scheduling for Conditional Branch Execution Onto Multi-Context Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-8 [Conf]
  55. Rafael Ruiz-Sautua, María C. Molina, Joé M. Mendias, Román Hermida
    Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  56. David Atienza, Pablo Garcia Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida
    HW-SW emulation framework for temperature-aware design in MPSoCs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:3, pp:- [Journal]
  57. José Luis Imaña, Román Hermida, Francisco Tirado
    Low Complexity Bit-Parallel Multipliers Based on a Class of Irreducible Pentanomials. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:12, pp:1388-1393 [Journal]
  58. Rafael Maestre, F. Kurdahl, Milagros Fernández, Román Hermida, Nader Bagherzadeh, Hartej Singh
    A formal approach to context scheduling for multicontext reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:173-185 [Journal]
  59. Rafael Maestre, Fadi J. Kurdahi, Milagros Fernández, Román Hermida, Nader Bagherzadeh, Hartej Singh
    A framework for reconfigurable computing: task scheduling and context management. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:858-873 [Journal]

  60. Using Speculative Functional Units in high level synthesis. [Citation Graph (, )][DBLP]


  61. Restricted Chaining and Fragmentation Techniques in Power Aware High Level Synthesis. [Citation Graph (, )][DBLP]


  62. Applying speculation techniques to implement functional units. [Citation Graph (, )][DBLP]


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