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Sandeep K. Shukla: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jean-Pierre Talpin, David Berner, Sandeep K. Shukla, Paul Le Guernic, Abdoulaye Gamatié, Rajesh Gupta
    A Behavioral Type Inference System for Compositional System-on-Chip Design. [Citation Graph (0, 0)][DBLP]
    ACSD, 2004, pp:47-56 [Conf]
  2. Jean-Pierre Talpin, Paul Le Guernic, Sandeep K. Shukla, Rajesh K. Gupta, Frederic Doucet
    Polychrony for Formal Refinement-Checking in a System-Level Design Methodology. [Citation Graph (0, 0)][DBLP]
    ACSD, 2003, pp:9-19 [Conf]
  3. David Berner, Jean-Pierre Talpin, Paul Le Guernic, Sandeep K. Shukla
    Modular design through component abstraction. [Citation Graph (0, 0)][DBLP]
    CASES, 2004, pp:202-211 [Conf]
  4. Sandeep K. Shukla, Harry B. Hunt III, Daniel J. Rosenkrantz
    HORNSAT, Model Checking, Verification and games (Extended Abstract). [Citation Graph (0, 0)][DBLP]
    CAV, 1996, pp:99-110 [Conf]
  5. Rajesh K. Gupta, Shishpal Rawat, Sandeep K. Shukla, Brian Bailey, Daniel K. Beece, Masahiro Fujita, Carl Pixley, John O'Leary, Fabio Somenzi
    Formal verification - prove it or pitch it. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:710-711 [Conf]
  6. Debayan Bhaduri, Sandeep K. Shukla, Deji Coker, Valerie Taylor, Paul Graham, Maya Gokhale
    A hybrid framework for design and analysis of fault-tolerant architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:335-336 [Conf]
  7. Frederic Doucet, Sandeep K. Shukla, Rajesh K. Gupta
    Introspection in System-Level Language Frameworks: Meta-Level vs. Integrated. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10382-10387 [Conf]
  8. Frederic Doucet, Sandeep K. Shukla, Rajesh K. Gupta, Masato Otsuka
    An Environment for Dynamic Component Composition for Efficient Co-Design . [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:736-743 [Conf]
  9. Sandy Irani, Rajesh K. Gupta, Sandeep K. Shukla
    Competitive Analysis of Dynamic Power Management Strategies for Systems with Multiple Power Savings States. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:117-123 [Conf]
  10. Mohammad Reza Mousavi, Paul Le Guernic, Jean-Pierre Talpin, Sandeep K. Shukla, Twan Basten
    Modeling and Validating Globally Asynchronous Design in Synchronous Frameworks. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:384-389 [Conf]
  11. Hiren D. Patel, Sandeep K. Shukla, Reinaldo A. Bergamaschi
    Heterogeneous behavioral hierarchy for system level designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:565-570 [Conf]
  12. Nick Savoiu, Sandeep K. Shukla, Rajesh K. Gupta
    Automated Concurrency Re-Assignment in High Level System Models for Efficient System-Level Simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:875-883 [Conf]
  13. Patrick Schaumont, Sandeep K. Shukla, Ingrid Verbauwhede
    Design with race-free hardware semantics. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:571-576 [Conf]
  14. Jean-Pierre Talpin, Paul Le Guernic, Sandeep K. Shukla, Rajesh K. Gupta, Frederic Doucet
    Polychrony for Refinement-Based Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11172-11173 [Conf]
  15. Debayan Bhaduri, Sandeep K. Shukla
    NANOPRISM: a tool for evaluating granularity vs. reliability trade-offs in nano architectures. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:109-112 [Conf]
  16. Hiren D. Patel, Sandeep K. Shukla
    Towards a heterogeneous simulation kernel for system level models: a SystemC kernel for synchronous data flow models. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:248-253 [Conf]
  17. Sandeep K. Shukla, Frederic Doucet, Rajesh K. Gupta
    Structured Component Composition Frameworks for Embedded System Design. [Citation Graph (0, 0)][DBLP]
    HiPC, 2002, pp:663-678 [Conf]
  18. Sandeep K. Shukla, Harry B. Hunt III, Daniel J. Rosenkrantz, Richard Edwin Stearns
    On the Complexity of Relational Problems for Finite State Processes (Extended Abstract). [Citation Graph (0, 0)][DBLP]
    ICALP, 1996, pp:466-477 [Conf]
  19. Rajesh K. Gupta, Sandy Irani, Sandeep K. Shukla
    Formal Methods for Dynamic Power Management. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:874-882 [Conf]
  20. Radu Cornea, Nikil D. Dutt, Rajesh K. Gupta, Ingolf Krüger, Alexandru Nicolau, Douglas C. Schmidt, Sandeep K. Shukla
    FORGE: A Framework for Optimization of Distributed Embedded Systems Software. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:208- [Conf]
  21. Shivajit Mohapatra, Radu Cornea, Hyunok Oh, Kyoungwoo Lee, Minyoung Kim, Nikil D. Dutt, Rajesh Gupta, Alexandru Nicolau, Sandeep K. Shukla, Nalini Venkatasubramanian
    A Cross-Layer Approach for Power-Performance Optimization in Distributed Mobile Systems. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  22. Rajesh K. Gupta, Sandeep K. Shukla, Nick Savoiu
    Efficient Simulation of Synthesis-Oriented System Level Designs. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:168-173 [Conf]
  23. Frederic Doucet, Rajesh K. Gupta, Masato Otsuka, Patrick Schaumont, Sandeep K. Shukla
    Interoperability as a design issue in C++ based modeling environments. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:87-92 [Conf]
  24. Debayan Bhaduri, Sandeep K. Shukla
    NANOLAB: A Tool for Evaluating Reliability of Defect-Tolerant Nano Architectures. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:25-31 [Conf]
  25. Hiren D. Patel, Sandeep K. Shukla
    Towards a Heterogeneous Simulation Kernel for System Level Models: A SystemC Kernel for Synchronous Data Flow Models. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:241-242 [Conf]
  26. Nick Savoiu, Sandeep K. Shukla, Rajesh K. Gupta
    Concurrency in System Level Design: Conflict Between Simulation and Synthesis Goals. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:407-411 [Conf]
  27. Nicolae Savoiu, Sandeep K. Shukla, Rajesh K. Gupta
    Improving SystemC simulation through Petri net reductions. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2005, pp:131-140 [Conf]
  28. Patrick Schaumont, Sandeep K. Shukla, Ingrid Verbauwhede
    Extended abstract: a race-free hardware modeling language. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2005, pp:255-256 [Conf]
  29. Sandeep K. Shukla, Tevfik Bultan, Constance L. Heitmeyer
    Panel: given that hardware verification has been an uphill battle, what is the future of software verification? [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2004, pp:157-158 [Conf]
  30. Rajesh K. Gupta, Sandeep K. Shukla
    Should the space of implementation possibilities be determined by the abilities of high-level synthesis and validation? [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2003, pp:277-0 [Conf]
  31. Grant Martin, Sandeep K. Shukla
    Hierarchical and Incremental Verification for System Level Design: Challenges and Accomplishments. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2003, pp:97-0 [Conf]
  32. Sandeep K. Shukla
    Teaching Game Theory for Computer Engineering. [Citation Graph (0, 0)][DBLP]
    MSE, 2005, pp:41-42 [Conf]
  33. David Berner, Hiren D. Patel, Deepak Mathaikutty, Sandeep K. Shukla
    Automated Extraction of Structural Information from SystemC-based IP for Validation. [Citation Graph (0, 0)][DBLP]
    MTV, 2005, pp:99-104 [Conf]
  34. Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, David Berner
    Extreme Formal Modeling (XFM) for Hardware Models. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:30-35 [Conf]
  35. Hiren D. Patel, Sandeep K. Shukla
    Deep vs. Shallow, Kernel vs. Language--What is Better for Heterogeneous Modeling in {SystemC}?. [Citation Graph (0, 0)][DBLP]
    MTV, 2006, pp:68-75 [Conf]
  36. Sandeep K. Shukla, Harry B. Hunt III, Daniel J. Rosenkrantz, S. S. Ravi, Richard Edwin Stearns
    I/O Automata Based Verification of Finite State Distributed Systems: Complexity Issues (Abstract). [Citation Graph (0, 0)][DBLP]
    PODC, 1996, pp:122- [Conf]
  37. Qing Guo, Paliath Narendran, Sandeep K. Shukla
    Unification and Matching in Process Algebras. [Citation Graph (0, 0)][DBLP]
    RTA, 1998, pp:91-105 [Conf]
  38. Sandy Irani, Sandeep K. Shukla, Rajesh K. Gupta
    Algorithms for power savings. [Citation Graph (0, 0)][DBLP]
    SODA, 2003, pp:37-46 [Conf]
  39. Luca Benini, Sandeep K. Shukla, Rajesh K. Gupta
    Architectural, System Level and Protocol Level Techniques for Power Optimization for Networked Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:18-0 [Conf]
  40. Gethin Norman, David Parker, Marta Z. Kwiatkowska, Sandeep K. Shukla
    Evaluating the Reliability of Defect-Tolerant Architectures for Nanotechnology with Probabilistic Model Checking. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:907-0 [Conf]
  41. Sandeep K. Shukla, Jean-Pierre Talpin, Stephen A. Edwards, Rajesh K. Gupta
    High Level Modeling and Validation Methodologies for Embedded Systems: Bridging the Productivity Gap. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:9-14 [Conf]
  42. Sreekumar V. Kodakara, Deepak Mathaikutty, Ajit Dingankar, Sandeep K. Shukla, David J. Lilja
    Model Based Test Generation for Microprocessor Architecture Validation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:465-472 [Conf]
  43. Debayan Bhaduri, Sandeep K. Shukla, Paul Graham, Maya Gokhale
    Scalable techniques and tools for reliability analysis of large circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:705-710 [Conf]
  44. R. Iris Bahar, Mehdi Baradaran Tahoori, Sandeep K. Shukla, Fabrizio Lombardi
    Guest Editors' Introduction: Challenges for Reliable Design at the Nanoscale. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:4, pp:295-297 [Journal]
  45. Sandeep K. Shukla, Carl Pixley, Gary Smith
    Guest Editors' Introduction: The True State of the Art of ESL Design. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:5, pp:335-337 [Journal]
  46. Hans-Joachim Wunderlich, Sandeep K. Shukla
    Panel Summaries. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:1, pp:65-66 [Journal]
  47. Juliana Küster Filipe, Iman Poernomo, Ralf Reussner, Sandeep K. Shukla
    Preface. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2004, v:108, n:, pp:1-2 [Journal]
  48. Juliana Küster Filipe, Iman Poernomo, Ralf Reussner, Sandeep K. Shukla
    Preface. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2005, v:141, n:3, pp:1-2 [Journal]
  49. Ken S. Stevens, Sandeep K. Shukla, Montek Singh, Jean-Pierre Talpin
    Preface. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2006, v:146, n:2, pp:1-3 [Journal]
  50. Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, David Berner, Jean-Pierre Talpin
    A Functional Programming Framework for Latency Insensitive Protocol Validation. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2006, v:146, n:2, pp:169-188 [Journal]
  51. Gethin Norman, David Parker, Marta Z. Kwiatkowska, Sandeep K. Shukla, Rajesh Gupta
    Using probabilistic model checking for dynamic power management. [Citation Graph (0, 0)][DBLP]
    Formal Asp. Comput., 2005, v:17, n:2, pp:160-176 [Journal]
  52. R. H. Hardin, Robert P. Kurshan, Sandeep K. Shukla, Moshe Y. Vardi
    A New Heuristic for Bad Cycle Detection Using BDDs. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2001, v:18, n:2, pp:131-140 [Journal]
  53. Sandeep K. Shukla, Michael Theobald
    Special issue on formal methods for globally asynchronous and locally synchronous (GALS) systems. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2006, v:28, n:2, pp:91-92 [Journal]
  54. Jean-Pierre Talpin, Paul Le Guernic, Sandeep K. Shukla, Frederic Doucet, Rajesh K. Gupta
    Formal Refinement Checking in a System-level Design Methodology. [Citation Graph (0, 0)][DBLP]
    Fundam. Inform., 2004, v:62, n:2, pp:243-273 [Journal]
  55. Jean-Pierre Talpin, Paul Le Guernic, Sandeep K. Shukla, Rajesh Gupta
    A Compositional Behavioral Modeling Framework for Embedded System Design and Conformance Checking. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2005, v:33, n:6, pp:613-643 [Journal]
  56. Syed Suhaib, Deepak Mathaikutty, David Berner, Sandeep K. Shukla
    Validating Families of Latency Insensitive Protocols. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:11, pp:1391-1401 [Journal]
  57. Frederic Doucet, Sandeep K. Shukla, Masato Otsuka, Rajesh K. Gupta
    BALBOA: a component-based design environment for system models. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:12, pp:1597-1612 [Journal]
  58. Gethin Norman, David Parker, Marta Z. Kwiatkowska, Sandeep K. Shukla
    Evaluating the reliability of NAND multiplexing with PRISM. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:10, pp:1629-1637 [Journal]
  59. Hiren D. Patel, Sandeep K. Shukla
    Towards a heterogeneous simulation kernel for system-level models: a SystemC kernel for synchronous data flow models. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:8, pp:1261-1271 [Journal]
  60. Hiren D. Patel, Deepak Mathaikutty, David Berner, Sandeep K. Shukla
    CARH: service-oriented architecture for validating system-level designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:8, pp:1458-1474 [Journal]
  61. Sandeep K. Shukla, Jean-Pierre Talpin
    Guest editorial: Special issue on models and methodologies for co-design of embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2005, v:4, n:2, pp:225-227 [Journal]
  62. Sandy Irani, Sandeep K. Shukla, Rajesh K. Gupta
    Online strategies for dynamic power management in systems with multiple power-saving states. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2003, v:2, n:3, pp:325-346 [Journal]
  63. Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, David Berner
    XFM: An incremental methodology for developing formal models. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:4, pp:589-609 [Journal]
  64. Sandy Irani, G. Singh, Sandeep K. Shukla, Rajesh K. Gupta
    An overview of the competitive and adversarial approaches to designing dynamic power management strategies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:12, pp:1349-1361 [Journal]
  65. Hiren D. Patel, Sandeep K. Shukla
    Model-driven Validation of SystemC Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:29-34 [Conf]
  66. Hiren D. Patel, Sandeep K. Shukla
    Tackling an abstraction gap: co-simulating SystemC DE with bluespec ESL. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:279-284 [Conf]
  67. Deepak Mathaikutty, Sandeep K. Shukla, Sreekumar V. Kodakara, David J. Lilja, Ajit Dingankar
    Design fault directed test generation for microprocessor validation. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:761-766 [Conf]
  68. Edgar G. Daylight, Sandeep K. Shukla
    Local Causal Reasoning of a Safety-Critical Subway System. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2007, pp:83-84 [Conf]
  69. G. Singh, Sandeep K. Shukla
    Low-power hardware synthesis from TRS-based specifications. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2006, pp:49-58 [Conf]
  70. Hiren D. Patel, Sandeep K. Shukla, E. Mednick, Rishiyur S. Nikhil
    A rule-based model of computation for SystemC: integrating SystemC and Bluespec for co-design. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2006, pp:39-48 [Conf]
  71. Deepak Mathaikutty, Sandeep K. Shukla
    Type Inference for IP Composition. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2007, pp:61-70 [Conf]
  72. Eric Simpson, Pengyuan Yu, Patrick Schaumont, Sumit Ahuja, Sandeep K. Shukla
    VT Matrix Multiply Design for MEMOCODE '07. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2007, pp:95-96 [Conf]
  73. Deepak Mathaikutty, Hiren D. Patel, Sandeep K. Shukla, Axel Jantsch
    EWD: A metamodeling driven customizable multi-MoC system modeling framework. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:3, pp:- [Journal]

  74. Complexity of Scheduling in Synthesizing Hardware from Concurrent Action Oriented Specifications. [Citation Graph (, )][DBLP]


  75. On the Difficulties of Concurrent-System Design, Illustrated with a 2×2 Switch Case Study. [Citation Graph (, )][DBLP]


  76. Power estimation methodology for a high-level synthesis framework. [Citation Graph (, )][DBLP]


  77. Coprocessor design space exploration using high level synthesis. [Citation Graph (, )][DBLP]


  78. Translating concurrent action oriented specifications to synchronous guarded actions. [Citation Graph (, )][DBLP]


  79. On the Deterministic Multi-threaded Software Synthesis from Polychronous Specifications. [Citation Graph (, )][DBLP]


  80. Model Checking Bluespec Specified Hardware Designs. [Citation Graph (, )][DBLP]


  81. Assertion-Based Modal Power Estimation. [Citation Graph (, )][DBLP]


  82. Verifying Compiler Based Refinement of BluespecTM. [Citation Graph (, )][DBLP]


  83. A Methodology for Power Aware High-Level Synthesis of Co-processors from Software Algorithms. [Citation Graph (, )][DBLP]


  84. Formal Transformation of a KPN Specification to a GALS Implementation. [Citation Graph (, )][DBLP]


  85. A Metamodeling based Framework for Architectural Modeling and Simulator Generation. [Citation Graph (, )][DBLP]


  86. MCF: A Metamodeling-based Visual Component Composition Framework. [Citation Graph (, )][DBLP]


  87. Mining Metadata for Composability of IPs from SystemC IP Library. [Citation Graph (, )][DBLP]


  88. Modelling Environment for Heterogeneous Systems based on MoCs. [Citation Graph (, )][DBLP]


  89. SystemCXML: An Exstensible SystemC Front end Using XML. [Citation Graph (, )][DBLP]


  90. Towards Behavioural Hierarchy Extensions for SystemC. [Citation Graph (, )][DBLP]


  91. A Functional Programming Framework of Heterogeneous Model of Computation for System Design. [Citation Graph (, )][DBLP]


  92. Model-Driven Engineering and Safety-Critical Embedded Software. [Citation Graph (, )][DBLP]


  93. Expressing the Behavior of Three Very Different Concurrent Systems by Using Natural Extensions of Separation Logic [Citation Graph (, )][DBLP]


  94. Guest Editors' Introduction: GALS Design and Validation. [Citation Graph (, )][DBLP]


  95. Metamodeling: An Emerging Representation Paradigm for System-Level Design. [Citation Graph (, )][DBLP]


  96. Metamodeling: What is it good for? [Citation Graph (, )][DBLP]


  97. Hardware Coprocessor Synthesis from an ANSI C Specification. [Citation Graph (, )][DBLP]


  98. Dataflow Architectures for GALS. [Citation Graph (, )][DBLP]


  99. Generating Multi-Threaded code from Polychronous Specifications. [Citation Graph (, )][DBLP]


  100. Preface. [Citation Graph (, )][DBLP]


  101. Modeling and Analyzing the Implementation of Latency-Insensitive Protocols Using the Polychrony Framework. [Citation Graph (, )][DBLP]


  102. An Analysis of the Composition of Synchronous Systems. [Citation Graph (, )][DBLP]


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