The SCEAS System
Navigation Menu
Introduction
Collection Based
Clustering
Ranking
Paper Based
Journals
Conferences
DB Status
Statistics
Search

Search the dblp DataBase

Title:
Author:
Rajesh K. Gupta: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jean-Pierre Talpin, Paul Le Guernic, Sandeep K. Shukla, Rajesh K. Gupta, Frederic Doucet
    Polychrony for Formal Refinement-Checking in a System-Level Design Methodology. [Citation Graph (0, 0)][DBLP]
    ACSD, 2003, pp:9-19 [Conf]
  2. Chalermek Intanagonwiwat, Rajesh K. Gupta, Amin Vahdat
    Declarative Resource Naming for Macroprogramming Wireless Networks of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ALGOSENSORS, 2006, pp:192-199 [Conf]
  3. Dinesh Ramanathan, Ravindra Jejurikar, Rajesh K. Gupta
    Timing driven co-design of networked embedded systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:117-122 [Conf]
  4. Prashant Arora, Rajesh K. Gupta
    Design and implementation of a hierarchical exception handling extension to systemC. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:80-84 [Conf]
  5. Ravindra Jejurikar, Rajesh K. Gupta
    Energy aware task scheduling with task synchronization for embedded real time systems. [Citation Graph (0, 0)][DBLP]
    CASES, 2002, pp:164-169 [Conf]
  6. Rajesh K. Gupta, Giovanni De Micheli
    Constrained software generation for hardware-software systems. [Citation Graph (0, 0)][DBLP]
    CODES, 1994, pp:56-63 [Conf]
  7. Jian Li, Rajesh K. Gupta
    HDL code restructuring using timed decision tables. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:131-135 [Conf]
  8. Cristiano Pereira, Jeremy Lau, Brad Calder, Rajesh K. Gupta
    Dynamic phase analysis for cycle-close trace generation. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:321-326 [Conf]
  9. Dinesh Ramanathan, Ali Dasdan, Rajesh K. Gupta
    Timing-driven HW/SW codesign based on task structuring and process timing simulation. [Citation Graph (0, 0)][DBLP]
    CODES, 1999, pp:203-207 [Conf]
  10. Jeffrey Namkung, Dohyung Kim, Rajesh K. Gupta, Igor Kozintsev, Jean-Yves Bouget, Carole Dulong
    Phase guided sampling for efficient parallel application simulation. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:187-192 [Conf]
  11. Samir Agrawal, Rajesh K. Gupta
    Data-Flow Assisted Behavioral Partitioning for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:709-712 [Conf]
  12. Ali Dasdan, Sandy Irani, Rajesh K. Gupta
    Efficient Algorithms for Optimum Cycle Mean and Optimum Cost to Time Ratio Problems. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:37-42 [Conf]
  13. Ali Dasdan, Dinesh Ramanathan, Rajesh K. Gupta
    Rate Derivation and Its Applications to Reactive, Real-Time Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:263-268 [Conf]
  14. Rajesh K. Gupta
    Analysis of Operation Delay and Execution Rate Constraints for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:601-604 [Conf]
  15. Rajesh K. Gupta, Claudionor José Nunes Coelho Jr., Giovanni De Micheli
    Synthesis and Simulation of Digital Systems Containing Interacting Hardware and Software Components. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:225-230 [Conf]
  16. Jian Li, Rajesh K. Gupta
    HDL Optimization Using Timed Decision Tables. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:51-54 [Conf]
  17. Rajesh K. Gupta, Shishpal Rawat, Sandeep K. Shukla, Brian Bailey, Daniel K. Beece, Masahiro Fujita, Carl Pixley, John O'Leary, Fabio Somenzi
    Formal verification - prove it or pitch it. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:710-711 [Conf]
  18. Rajesh K. Gupta, Shishpal Rawat, Ingrid Verbauwhede, Gérard Berry, Ramesh Chandra, Daniel Gajski, Kris Konigsfeld, Patrick Schaumont
    Panel: The Next HDL: If C++ is the Answer, What was the Question? [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:71-72 [Conf]
  19. Jian Li, Rajesh K. Gupta
    Limited Exception Modeling and Its Use in Presynthesis Optimizations. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:341-346 [Conf]
  20. Sumit Gupta, Nick Savoiu, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau, Timothy Kam, Michael Kishinevsky, Shai Rotem
    Coordinated transformations for high-level synthesis of high performance microprocessor blocks. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:898-903 [Conf]
  21. Sumit Gupta, Nick Savoiu, Sunwoo Kim, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau
    Speculation Techniques for High Level Synthesis of Control Intensive Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:269-272 [Conf]
  22. Ravindra Jejurikar, Rajesh K. Gupta
    Dynamic slack reclamation with procrastination scheduling in real-time embedded systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:111-116 [Conf]
  23. Ravindra Jejurikar, Cristiano Pereira, Rajesh K. Gupta
    Leakage aware dynamic voltage scaling for real-time embedded systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:275-280 [Conf]
  24. Stan Y. Liao, Steven W. K. Tjiang, Rajesh K. Gupta
    An Efficient Implementation of Reactivity for Modeling Hardware in the Scenic Design Environment. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:70-75 [Conf]
  25. Vijay Raghunathan, Mani B. Srivastava, Rajesh K. Gupta
    A survey of techniques for energy efficient on-chip communication. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:900-905 [Conf]
  26. Hans Van Antwerpen, Nikil D. Dutt, Rajesh K. Gupta, Shivajit Mohapatra, Cristiano Pereira, Nalini Venkatasubramanian, Ralph von Vignau
    Energy-Aware System Design for Wireless Multimedia. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1124-1131 [Conf]
  27. Jian Li, Rajesh K. Gupta
    An Algorithm To Determine Mutually Exclusive Operations In Behavioral Descriptions. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:457-0 [Conf]
  28. Frederic Doucet, Sandeep K. Shukla, Rajesh K. Gupta
    Introspection in System-Level Language Frameworks: Meta-Level vs. Integrated. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10382-10387 [Conf]
  29. Frederic Doucet, Sandeep K. Shukla, Rajesh K. Gupta, Masato Otsuka
    An Environment for Dynamic Component Composition for Efficient Co-Design . [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:736-743 [Conf]
  30. Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau
    Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10270-10275 [Conf]
  31. Sumit Gupta, Rajesh K. Gupta, Miguel Miranda, Francky Catthoor
    Analysis of High-Level Address Code Transformations for Programmable Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:9-13 [Conf]
  32. Sandy Irani, Rajesh K. Gupta, Sandeep K. Shukla
    Competitive Analysis of Dynamic Power Management Strategies for Systems with Multiple Power Savings States. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:117-123 [Conf]
  33. Dinesh Ramanathan, Rajesh K. Gupta
    System Level Online Power Management Algorithms. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:606-605 [Conf]
  34. Nick Savoiu, Sandeep K. Shukla, Rajesh K. Gupta
    Automated Concurrency Re-Assignment in High Level System Models for Efficient System-Level Simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:875-883 [Conf]
  35. Jean-Pierre Talpin, Paul Le Guernic, Sandeep K. Shukla, Rajesh K. Gupta, Frederic Doucet
    Polychrony for Refinement-Based Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11172-11173 [Conf]
  36. Weiyu Tang, Rajesh K. Gupta, Alexandru Nicolau
    Power Savings in Embedded Processors through Decode Filer Cache. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:443-448 [Conf]
  37. Ravindra Jejurikar, Rajesh K. Gupta
    Optimized Slowdown in Real-Time Task Systems. [Citation Graph (0, 0)][DBLP]
    ECRTS, 2004, pp:155-164 [Conf]
  38. Ravindra Jejurikar, Rajesh K. Gupta
    Energy Aware Non-Preemptive Scheduling for Hard Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    ECRTS, 2005, pp:21-30 [Conf]
  39. Nikhil Bansal, Sumit Gupta, Nikil D. Dutt, Alexandru Nicolau, Rajesh K. Gupta
    Interconnect-Aware Mapping of Applications to Coarse-Grain Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:891-899 [Conf]
  40. Sandeep K. Shukla, Frederic Doucet, Rajesh K. Gupta
    Structured Component Composition Frameworks for Embedded System Design. [Citation Graph (0, 0)][DBLP]
    HiPC, 2002, pp:663-678 [Conf]
  41. Amit Chowdhary, Sudhakar Kale, Phani K. Saripella, Naresh Sehgal, Rajesh K. Gupta
    A general approach for regularity extraction in datapath circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:332-339 [Conf]
  42. Ki-Seok Chung, Rajesh K. Gupta, C. L. Liu
    An algorithm for synthesis of system-level interface circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:442-447 [Conf]
  43. Rajesh K. Gupta, Sandy Irani, Sandeep K. Shukla
    Formal Methods for Dynamic Power Management. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:874-882 [Conf]
  44. Rajesh K. Gupta, Giovanni De Micheli
    Partitioning of Functional Models of Synchronous Digital Systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:216-219 [Conf]
  45. Rajesh K. Gupta, Mani B. Srivastava
    Design technology for building wireless systems (tutorial). [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:- [Conf]
  46. Jian Li, Rajesh K. Gupta
    Decomposition of timed decision tables and its use in presynthesis optimizations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:22-27 [Conf]
  47. Dinesh Ramanathan, Sandy Irani, Rajesh K. Gupta
    Latency Effects of System Level Power Management Algorithms. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:350-356 [Conf]
  48. Rajesh K. Gupta, Daniel Gajski, Randy Allen, Yatin Trivedi
    Opportunities and pitfalls in HDL-based system design. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:56-0 [Conf]
  49. Manev Luthra, Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau
    Interface Synthesis using Memory Mapping for an FPGA Platform. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:140-145 [Conf]
  50. Vinod Narayananan, David LaPotin, Rajesh K. Gupta, Gopalakrishnan Vijayan
    PEPPER - a timing driven early floorplanner. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:230-235 [Conf]
  51. Dinesh Ramanathan, Rajesh K. Gupta, Raymond Roth
    Interfacing Hardware and Software Using C++ Class Libraries. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:445-0 [Conf]
  52. Weiyu Tang, Rajesh K. Gupta, Alexandru Nicolau
    Design of a Predictive Filter Cache for Energy Savings in High Performance Processor Architectures. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:68-75 [Conf]
  53. Xingbin Zhang, Ali Dasdan, Martin Schulz, Rajesh K. Gupta, Andrew A. Chien
    Architectural Adaptation for Application-Specific Locality Optimization. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:150-156 [Conf]
  54. Alexander V. Veidenbaum, Weiyu Tang, Rajesh K. Gupta, Alexandru Nicolau, Xiaomei Ji
    Adapting cache line size to application behavior. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1999, pp:145-154 [Conf]
  55. Dan Nicolaescu, Xiaomei Ji, Alexander V. Veidenbaum, Alexandru Nicolau, Rajesh K. Gupta
    Compiler-Directed Cache Line Size Adaptivity. [Citation Graph (0, 0)][DBLP]
    Intelligent Memory Systems, 2000, pp:183-187 [Conf]
  56. Radu Cornea, Nikil D. Dutt, Rajesh K. Gupta, Ingolf Krüger, Alexandru Nicolau, Douglas C. Schmidt, Sandeep K. Shukla
    FORGE: A Framework for Optimization of Distributed Embedded Systems Software. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:208- [Conf]
  57. Xiaomei Ji, Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau, Rajesh K. Gupta
    Compiler-Directed Cache Assist Adaptivity. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2000, pp:88-104 [Conf]
  58. Weiyu Tang, Alexander V. Veidenbaum, Alexandru Nicolau, Rajesh K. Gupta
    Integrated I-cache Way Predictor and Branch Target Buffer to Reduce Energy Consumption. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2002, pp:120-132 [Conf]
  59. Ravindra Jejurikar, Rajesh K. Gupta
    Dynamic voltage scaling for systemwide energy minimization in real-time embedded systems. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:78-81 [Conf]
  60. Sumit Gupta, Nick Savoiu, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau
    Conditional speculation and its effects on performance and area for high-level snthesis. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:171-176 [Conf]
  61. Rajesh K. Gupta, Sandeep K. Shukla, Nick Savoiu
    Efficient Simulation of Synthesis-Oriented System Level Designs. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:168-173 [Conf]
  62. Frederic Doucet, Rajesh K. Gupta, Masato Otsuka, Patrick Schaumont, Sandeep K. Shukla
    Interoperability as a design issue in C++ based modeling environments. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:87-92 [Conf]
  63. Wolfgang Rosenstiel, Brian Bailey, Masahiro Fujita, Guang R. Gao, Rajesh K. Gupta, Preeti Ranjan Panda
    New design paradigms. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:94- [Conf]
  64. Vivek Sinha, Frederic Doucet, Chuck Siska, Rajesh K. Gupta, Stan Y. Liao, Abhijit Ghosh
    YAML: A Tool for Hardware Design Visualization and Capture. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:9-17 [Conf]
  65. Nick Savoiu, Sandeep K. Shukla, Rajesh K. Gupta
    Concurrency in System Level Design: Conflict Between Simulation and Synthesis Goals. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:407-411 [Conf]
  66. Ravindra Jejurikar, Rajesh K. Gupta
    Procrastination scheduling in fixed priority real-time systems. [Citation Graph (0, 0)][DBLP]
    LCTES, 2004, pp:57-66 [Conf]
  67. Nicolae Savoiu, Sandeep K. Shukla, Rajesh K. Gupta
    Improving SystemC simulation through Petri net reductions. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2005, pp:131-140 [Conf]
  68. Rajesh K. Gupta, Sandeep K. Shukla
    Should the space of implementation possibilities be determined by the abilities of high-level synthesis and validation? [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2003, pp:277-0 [Conf]
  69. Trevor Pering, Yuvraj Agarwal, Rajesh K. Gupta, Roy Want
    CoolSpots: reducing the power consumption of wireless mobile devices with multiple radio interfaces. [Citation Graph (0, 0)][DBLP]
    MobiSys, 2006, pp:220-232 [Conf]
  70. Sandy Irani, Sandeep K. Shukla, Rajesh K. Gupta
    Algorithms for power savings. [Citation Graph (0, 0)][DBLP]
    SODA, 2003, pp:37-46 [Conf]
  71. Luca Benini, Sandeep K. Shukla, Rajesh K. Gupta
    Architectural, System Level and Protocol Level Techniques for Power Optimization for Networked Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:18-0 [Conf]
  72. Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau
    SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:461-466 [Conf]
  73. Luciano Lavagno, Sujit Dey, Rajesh K. Gupta
    Specification, Modeling and Design Tools for System-on-Chip (Tutorial Abstract). [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:21-23 [Conf]
  74. Sandeep K. Shukla, Jean-Pierre Talpin, Stephen A. Edwards, Rajesh K. Gupta
    High Level Modeling and Validation Methodologies for Embedded Systems: Bridging the Productivity Gap. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:9-14 [Conf]
  75. Zhang Yang, Rajesh K. Gupta
    A Case Analysis of System Partitioning and Its Relationship To High-Level Synthesis Tasks. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:442-448 [Conf]
  76. Rajesh K. Gupta
    Driving Research in System-Chip Design Technology. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2003, v:36, n:7, pp:95-97 [Journal]
  77. Rajesh K. Gupta, Claudionor José Nunes Coelho Jr., Giovanni De Micheli
    Program Implementation Schemes for Hardware-Software Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1994, v:27, n:1, pp:48-55 [Journal]
  78. Amit Chowdhary, Rajesh K. Gupta
    A Methodology for Synthesis of Data Path Circuitse. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:6, pp:90-100 [Journal]
  79. Rajesh K. Gupta
    Verification synergies. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:6, pp:457- [Journal]
  80. Rajesh K. Gupta
    Global competitiveness, outsourcing, and education in the semiconductor industry. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:1, pp:5-6 [Journal]
  81. Rajesh K. Gupta
    FPGA-enabled computing architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:2, pp:81- [Journal]
  82. Rajesh K. Gupta
    The other face of design for manufacturability. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:3, pp:193- [Journal]
  83. Rajesh K. Gupta
    Nanotechnology: Where science of the small meets math of the large. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:4, pp:289- [Journal]
  84. Rajesh K. Gupta
    On-chip networks. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:5, pp:393- [Journal]
  85. Rajesh K. Gupta
    Going 3D: Silicon and D&T. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:6, pp:493-494 [Journal]
  86. Rajesh K. Gupta, Stan Y. Liao
    Using a Programming Language for Digital System Design. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:2, pp:72-80 [Journal]
  87. Rajesh K. Gupta, Giovanni De Micheli
    Hardware-Software Cosynthesis for Digital Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1993, v:10, n:3, pp:29-41 [Journal]
  88. Rajesh K. Gupta, Yervant Zorian
    Introducing Core-Based System Design. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:4, pp:15-25 [Journal]
  89. Yervant Zorian, Rajesh K. Gupta
    Design and Test of Core-Based Systems on Chips. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:4, pp:14-0 [Journal]
  90. Frederic Doucet, Massimiliano Menarini, Ingolf H. Krüger, Rajesh K. Gupta, Jean-Pierre Talpin
    A Verification Approach for GALS Integration of Synchronous Components. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2006, v:146, n:2, pp:105-131 [Journal]
  91. Jean-Pierre Talpin, Paul Le Guernic, Sandeep K. Shukla, Frederic Doucet, Rajesh K. Gupta
    Formal Refinement Checking in a System-level Design Methodology. [Citation Graph (0, 0)][DBLP]
    Fundam. Inform., 2004, v:62, n:2, pp:243-273 [Journal]
  92. Paolo D'Alberto, Alexandru Nicolau, Alexander V. Veidenbaum, Rajesh K. Gupta
    Line Size Adaptivity Analysis of Parameterized Loop Nests for Direct Mapped Data Cache. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:2, pp:185-197 [Journal]
  93. Amit Chowdhary, Sudhakar Kale, Phani K. Saripella, Naresh Sehgal, Rajesh K. Gupta
    Extraction of functional regularity in datapath circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1279-1296 [Journal]
  94. Ali Dasdan, Rajesh K. Gupta
    Faster maximum and minimum mean cycle algorithms for system-performance analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:10, pp:889-899 [Journal]
  95. Frederic Doucet, Sandeep K. Shukla, Masato Otsuka, Rajesh K. Gupta
    BALBOA: a component-based design environment for system models. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:12, pp:1597-1612 [Journal]
  96. Rajesh K. Gupta, Giovanni De Micheli
    Specification and analysis of timing constraints for embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:3, pp:240-256 [Journal]
  97. Sumit Gupta, Nicolae Savoiu, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau
    Using global code motions to improve the quality of results for high-level synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:2, pp:302-312 [Journal]
  98. Ravindra Jejurikar, Rajesh K. Gupta
    Energy-aware task scheduling with task synchronization for embedded real-time systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1024-1037 [Journal]
  99. Dinesh Ramanathan, Sandy Irani, Rajesh K. Gupta
    An analysis of system level power management algorithms and theireffects on latency. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:3, pp:291-305 [Journal]
  100. Sandy Irani, Sandeep K. Shukla, Rajesh K. Gupta
    Online strategies for dynamic power management in systems with multiple power-saving states. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2003, v:2, n:3, pp:325-346 [Journal]
  101. Ali Dasdan, Dinesh Ramanathan, Rajesh K. Gupta
    A timing-driven design and validation methodology for embedded real-time systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:4, pp:533-553 [Journal]
  102. Sumit Gupta, Rajesh K. Gupta, Nikil D. Dutt, Alexandru Nicolau
    Coordinated parallelizing compiler optimizations and high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2004, v:9, n:4, pp:441-470 [Journal]
  103. Anmol Mathur, Ali Dasdan, Rajesh K. Gupta
    Rate analysis for embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:3, pp:408-436 [Journal]
  104. Sandy Irani, G. Singh, Sandeep K. Shukla, Rajesh K. Gupta
    An overview of the competitive and adversarial approaches to designing dynamic power management strategies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:12, pp:1349-1361 [Journal]
  105. Arun Kejariwal, Sumit Gupta, Alexandru Nicolau, Nikil D. Dutt, Rajesh K. Gupta
    Energy efficient watermarking on mobile devices using proxy-based partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:6, pp:625-636 [Journal]
  106. Frederic Doucet, Ingolf Krüger, Rajesh K. Gupta, R. K. Shyamasundar
    Compositional interaction specifications for SystemC. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2006, pp:201- [Conf]
  107. Yuvraj Agarwal, Ranveer Chandra, Alec Wolman, Paramvir Bahl, Kevin Chin, Rajesh K. Gupta
    Wireless wakeups revisited: energy management for voip over wi-fi smartphones. [Citation Graph (0, 0)][DBLP]
    MobiSys, 2007, pp:179-191 [Conf]
  108. Zhong-Yi Jin, Curt Schurgers, Rajesh K. Gupta
    An Embedded Platform with Duty-Cycled Radio and Processing Subsystems for Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:421-430 [Conf]

  109. RATAN: A tool for rate analysis and rate constraint debugging for embedded systems. [Citation Graph (, )][DBLP]


  110. Improving the Data Delivery Latency in Sensor Networks with Controlled Mobility. [Citation Graph (, )][DBLP]


  111. Reactivity in SystemC Transaction-Level Models. [Citation Graph (, )][DBLP]


  112. Optimizing Energy-Latency Trade-Off in Sensor Networks with Controlled Mobility. [Citation Graph (, )][DBLP]


  113. Improving the speed and scalability of distributed simulations of sensor networks. [Citation Graph (, )][DBLP]


Search in 0.007secs, Finished in 0.606secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
Introduction Collection Based Clustering Ranking Paper Based Journals Conferences DB Status Statistics Search
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002