The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Axel Jantsch: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Axel Jantsch
    Models of Computation for Networks on Chip. [Citation Graph (0, 0)][DBLP]
    ACSD, 2006, pp:165-178 [Conf]
  2. Tiberiu Seceleanu, Axel Jantsch
    Communicating with Synchronized Environments. [Citation Graph (0, 0)][DBLP]
    ACSD, 2006, pp:15-24 [Conf]
  3. Zhonghai Lu, Axel Jantsch, Ingo Sander
    Feasibility analysis of messages for on-chip networks using wormhole routing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:960-964 [Conf]
  4. Iyad Al Khatib, Davide Bertozzi, Francesco Poletti, Luca Benini, Axel Jantsch, Mohamed Bechara, Hasan Khalifeh, Mazen Hajjar, Rustam Nabiev, Sven Jonsson
    MPSoC ECG biochip: a multiprocessor system-on-chip for real-time human heart monitoring and analysis. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2006, pp:21-28 [Conf]
  5. Per Bjuréus, Mikael Millberg, Axel Jantsch
    FPGA resource and timing estimation from Matlab execution traces. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:31-36 [Conf]
  6. Axel Jantsch, Ingo Sander
    On the roles of functions and objects in system specification. [Citation Graph (0, 0)][DBLP]
    CODES, 2000, pp:8-12 [Conf]
  7. Axel Jantsch, Ingo Sander, Wenbiao Wu
    The usage of stochastic processes in embedded system specifications. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:5-10 [Conf]
  8. Tarvo Raudvere, Ingo Sander, Ashish Kumar Singh, Axel Jantsch
    Verification of design decisions in ForSyDe. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:176-181 [Conf]
  9. Ingo Sander, Axel Jantsch
    System synthesis utilizing a layered functional model. [Citation Graph (0, 0)][DBLP]
    CODES, 1999, pp:136-140 [Conf]
  10. Heiko Zimmer, Axel Jantsch
    A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:188-193 [Conf]
  11. Abhijit K. Deb, Axel Jantsch, Johnny Öberg
    System design for DSP applications in transaction level modeling paradigm. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:466-471 [Conf]
  12. Iyad Al Khatib, Francesco Poletti, Davide Bertozzi, Luca Benini, Mohamed Bechara, Hasan Khalifeh, Axel Jantsch, Rustam Nabiev
    A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: architectural design space exploration. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:125-130 [Conf]
  13. Ingo Sander, Axel Jantsch
    Transformation based communication and clock domain refinement for system design. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:281-286 [Conf]
  14. Per Bjuréus, Axel Jantsch
    MASCOT: A Specification and Cosimulation Method Integrating Data and Control Flow. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:161-168 [Conf]
  15. Abhijit K. Deb, Axel Jantsch, Johnny Öberg
    System Design for DSP Applications Using the MASIC Methodology. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:630-635 [Conf]
  16. Abhijit K. Deb, Johnny Öberg, Axel Jantsch
    Simulation and Analysis of Embedded DSP Systems Using MASIC Methodology. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11100-11101 [Conf]
  17. Axel Jantsch, Per Bjuréus
    Composite Signal Flow: A Computational Model Combining Events, Sampled Streams, and Vectors. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:154-160 [Conf]
  18. Axel Jantsch, Shashi Kumar, Ahmed Hemani
    The Rugby Model: A Conceptual Frame for the Study of Modelling, Analysis and Synthesis Concepts of Electronic Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:256-262 [Conf]
  19. Mikael Millberg, Erland Nilsson, Rikard Thid, Axel Jantsch
    Guaranteed Bandwidth Using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:890-895 [Conf]
  20. Erland Nilsson, Mikael Millberg, Johnny Öberg, Axel Jantsch
    Load Distribution with the Proximity Congestion Awareness in a Network on Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11126-11127 [Conf]
  21. Mattias O'Nils, Axel Jantsch
    Operating System Sensitive Device Driver Synthesis from Implementation Independent Protocol Specification. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:562-567 [Conf]
  22. Tarvo Raudvere, Ashish Kumar Singh, Ingo Sander, Axel Jantsch
    Polynomial Abstraction for Verification of Sequentially Implemented Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:690-691 [Conf]
  23. Ingo Sander, Axel Jantsch, Zhonghai Lu
    Development and Application of Design Transformations in ForSyDe. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10364-10369 [Conf]
  24. Axel Jantsch
    NoCs: A new Contract between Hardware and Software. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:10-16 [Conf]
  25. Zhonghai Lu, Ingo Sander, Axel Jantsch
    Towards Performance-Oriented Pattern-Based Refinement of Synchronous Models onto NoC Communication. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:37-44 [Conf]
  26. Rikard Thid, Ingo Sander, Axel Jantsch
    Flexible Bus and NoC Performance Analysis with Configurable Synthetic Workloads. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:681-688 [Conf]
  27. Guang Liang, Axel Jantsch
    Adaptive Power Management for the On-Chip Communication Network. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:649-656 [Conf]
  28. Sandro Penolazzi, Axel Jantsch
    A High Level Power Model for the Nostrum NoC. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:673-676 [Conf]
  29. Mattias O'Nils, Johnny Öberg, Axel Jantsch
    Grammar Based Modelling and Synthesis of Device Drivers and Bus Interfaces. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10055-10058 [Conf]
  30. Johan Ditmar, Kjell Torkelsson, Axel Jantsch
    A Dynamically Reconfigurable FPGA-Based Content Addressable Memory for Internet Protocol Characterization. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:19-28 [Conf]
  31. Jouni Isoaho, Axel Jantsch, Hannu Tenhunen
    DSP Development with Full-Speed Prototyping Based on HW/SW Codesign Techniques. [Citation Graph (0, 0)][DBLP]
    FPL, 1994, pp:318-320 [Conf]
  32. Zhonghai Lu, Mingchen Zhong, Axel Jantsch
    Evaluation of on-chip networks using deflection routing. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:296-301 [Conf]
  33. Tarvo Raudvere, Ingo Sander, Axel Jantsch
    A synchronization algorithm for local temporal refinements in perfectly synchronous models with nested feedback loops. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:353-358 [Conf]
  34. Tarvo Raudvere, Ashish Kumar Singh, Ingo Sander, Axel Jantsch
    System level verification of digital signal processing applications based on the polynomial abstraction technique. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:285-290 [Conf]
  35. Axel Jantsch, Robert Lauter, Arseni Vitkovski
    Power analysis of link level and end-to-end data protection in networks on chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1770-1773 [Conf]
  36. Per Bjuréus, Axel Jantsch
    Performance analysis with confidence intervals for embedded software processes. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:45-50 [Conf]
  37. Abhijit K. Deb, Johnny Öberg, Axel Jantsch
    Control and communication performance analysis of embedded DSP systems in the MASIC methodology. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:274-273 [Conf]
  38. Ingo Sander, Axel Jantsch, Zhonghai Lu
    A Case Study of Hardware and Software Synthesis in ForSyDe. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:86-91 [Conf]
  39. Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnny Öberg, Juha-Pekka Soininen, Martti Forsell, Kari Tiensyrjä, Ahmed Hemani
    A Network on Chip Architecture and Design Methodology. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2002, pp:117-124 [Conf]
  40. Zhonghai Lu, Bei Yin, Axel Jantsch
    Connection-oriented Multicasting in Wormhole-switched Networks on Chip. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:205-2110 [Conf]
  41. Zhonghai Lu, Axel Jantsch
    Traffic Configuration for Evaluating Networks on Chips. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2005, pp:535-540 [Conf]
  42. Abhijit K. Deb, Johnny Öberg, Axel Jantsch
    Simulation and Analysis of Embedded DSP Systems Using Petri Nets. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2003, pp:64-70 [Conf]
  43. Dinesh Pamunuwa, Johnny Öberg, Li-Rong Zheng, Mikael Millberg, Axel Jantsch
    Layout, Performance and Power Trade-Offs in Mesh-Based Network-on-Chip Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:362-0 [Conf]
  44. Mikael Millberg, Erland Nilsson, Rikard Thid, Shashi Kumar, Axel Jantsch
    The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:693-696 [Conf]
  45. Mattias O'Nils, Axel Jantsch
    Synthesis of DMA Controllers from Architecture Independent Descriptions of HW/SW Communication Protocols. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:138-145 [Conf]
  46. Johnny Öberg, Jouni Isoaho, Peeter Ellervee, Axel Jantsch, Ahmed Hemani
    A Rule-Based Approach for Improving Allocation of Filter Structures in HLS. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:133-139 [Conf]
  47. Johnny Öberg, Axel Jantsch, Anshul Kumar
    An Object-Oriented Concept for Intelligent Library Functions. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:355-358 [Conf]
  48. Ingo Sander, Axel Jantsch
    Formal System Design Based on the Synchrony Hypothesis, Functional Models and Skeletons. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:318-323 [Conf]
  49. Juha-Pekka Soininen, Axel Jantsch, Martti Forsell, Antti Pelkonen, Jari Kreku, Shashi Kumar
    Extending Platform-Based Design to Network on Chip Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:401-0 [Conf]
  50. Bengt Svantesson, Ahmed Hemani, Peeter Ellervee, Adam Postula, Johnny Öberg, Axel Jantsch, Hannu Tenhunen
    A Novell Allocation Strategy for Control and Memory Intensive Telecommunication Circiuts. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:23-28 [Conf]
  51. Axel Jantsch, Shashi Kumar, Ahmed Hemani
    A Metamodel for Studying Concepts in Electronic System Design. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:3, pp:78-85 [Journal]
  52. Dinesh Pamunuwa, Johnny Öberg, Li-Rong Zheng, Mikael Millberg, Axel Jantsch, Hannu Tenhunen
    A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime. [Citation Graph (0, 0)][DBLP]
    Integration, 2004, v:38, n:1, pp:3-17 [Journal]
  53. Axel Jantsch, Johnny Öberg, Hannu Tenhunen
    Special issue on networks on chip. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2004, v:50, n:2-3, pp:61-63 [Journal]
  54. Ingo Sander, Axel Jantsch
    System modeling and transformational design refinement in ForSyDe [formal system design]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:17-32 [Journal]
  55. Zhonghai Lu, Ming Liu, Axel Jantsch
    Layered Switching for Networks on Chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:122-127 [Conf]
  56. Zhonghai Lu, Jonas Sicking, Ingo Sander, Axel Jantsch
    Using Synchronizers for Refining Synchronous Communication onto Hardware/Software Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2007, pp:143-149 [Conf]
  57. Per Badlund, Axel Jantsch
    An Analytical Approach for Dimensioning Mixed Traffic Networks. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:215- [Conf]
  58. Mikael Millberg, Axel Jantsch
    A Study of NoC Exit Strategies. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:217- [Conf]
  59. Cristian Grecu, André Ivanov, Partha Pratim Pande, Axel Jantsch, Erno Salminen, Ümit Y. Ogras, Radu Marculescu
    Towards Open Network-on-Chip Benchmarks. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:205- [Conf]
  60. Weixing Wang, Axel Jantsch
    An algorithm for electing cluster heads based on maximum residual energy. [Citation Graph (0, 0)][DBLP]
    IWCMC, 2006, pp:1465-1470 [Conf]
  61. Deepak Mathaikutty, Hiren D. Patel, Sandeep K. Shukla, Axel Jantsch
    EWD: A metamodeling driven customizable multi-MoC system modeling framework. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:3, pp:- [Journal]
  62. Per Bjuréus, Axel Jantsch
    Modeling of mixed control and dataflow systems in MASCOT. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:690-703 [Journal]

  63. Performance analysis and design space exploration for high-end biomedical applications: challenges and solutions. [Citation Graph (, )][DBLP]


  64. Synchronization after design refinements with sensitive delay elements. [Citation Graph (, )][DBLP]


  65. Heterogeneous System-level Specification Using SystemC. [Citation Graph (, )][DBLP]


  66. Priority based forced requeue to reduce worst-case latencies for bursty traffic. [Citation Graph (, )][DBLP]


  67. Flow regulation for on-chip communication. [Citation Graph (, )][DBLP]


  68. Buffer minimization of real-time streaming applications scheduling on hybrid CPU/FPGA architectures. [Citation Graph (, )][DBLP]


  69. Supporting Distributed Shared Memory on multi-core Network-on-Chips using a dual microcoded controller. [Citation Graph (, )][DBLP]


  70. Pareto efficient design for reconfigurable streaming applications on CPU/FPGAs. [Citation Graph (, )][DBLP]


  71. FPGA-based adaptive computing for correlated multi-stream processing. [Citation Graph (, )][DBLP]


  72. Optimal regulation of traffic flows in networks-on-chip. [Citation Graph (, )][DBLP]


  73. Cluster-based Simulated Annealing for Mapping Cores onto 2D Mesh Networks on Chip. [Citation Graph (, )][DBLP]


  74. Increasing NoC Performance and Utilisation using a Dual Packet Exit Strategy. [Citation Graph (, )][DBLP]


  75. System-on-an-FPGA Design for Real-time Particle Track Recognition and Reconstruction in Physics Experiments. [Citation Graph (, )][DBLP]


  76. Energy efficient streaming applications with guaranteed throughput on MPSoCs. [Citation Graph (, )][DBLP]


  77. Network Calculus Applied to Verification of Memory Access Performance in SoCs. [Citation Graph (, )][DBLP]


  78. Performance analysis of reconfiguration in adaptive real-time streaming applications. [Citation Graph (, )][DBLP]


  79. Hardware/software partitioning and minimizing memory interface traffic. [Citation Graph (, )][DBLP]


  80. The ANDRES Project: Analysis and Design of Run-Time Reconfigurable, Heterogeneous Systems. [Citation Graph (, )][DBLP]


  81. ATCA-based computation platform for data acquisition and triggering in particle physics experiments. [Citation Graph (, )][DBLP]


  82. Run-time Partial Reconfiguration speed investigation and architectural design space exploration. [Citation Graph (, )][DBLP]


  83. Slot allocation using logical networks for TDM virtual-circuit configuration for network-on-chip. [Citation Graph (, )][DBLP]


  84. High-level estimation and trade-off analysis for adaptive real-time systems. [Citation Graph (, )][DBLP]


  85. A Worst Case Performance Model for TDM Virtual Circuit in NoCs. [Citation Graph (, )][DBLP]


  86. Analytical Evaluation of Retransmission Schemes in Wireless Sensor Networks. [Citation Graph (, )][DBLP]


  87. Scalability of network-on-chip communication architecture for 3-D meshes. [Citation Graph (, )][DBLP]


  88. Traffic Splitting with Network Calculus for Mesh Sensor Networks. [Citation Graph (, )][DBLP]


  89. Modelling Environment for Heterogeneous Systems based on MoCs. [Citation Graph (, )][DBLP]


  90. Refinement of Perfectly Synchronous Communication Model. [Citation Graph (, )][DBLP]


  91. A Reconfigurable Design Framework for FPGA Adaptive Computing. [Citation Graph (, )][DBLP]


  92. Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh. [Citation Graph (, )][DBLP]


  93. DATE 07 workshop on diagnostic services in NoCs. [Citation Graph (, )][DBLP]


  94. Modelling Adaptive Systems in ForSyDe. [Citation Graph (, )][DBLP]


Search in 0.115secs, Finished in 0.120secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002