The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Sunan Tugsinavisut: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sunan Tugsinavisut, Roger Su, Peter A. Beerel
    High-level Synthesis for Highly Concurrent Hardware Systems. [Citation Graph (0, 0)][DBLP]
    ACSD, 2006, pp:79-90 [Conf]
  2. Sunan Tugsinavisut, Peter A. Beerel
    Control Circuit Templates for Asynchronous Bundled-Data Pipelines. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1098- [Conf]
  3. Sunan Tugsinavisut, Suwicha Jirayucharoensak, Peter A. Beerel
    An asynchronous pipeline comparisons with application to DCT matrix-vector multiplication. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:361-364 [Conf]
  4. Sangyun Kim, Sunan Tugsinavisut, Peter A. Beerel
    Reducing probabilistic timed petri nets for asynchronous architectural analysis. [Citation Graph (0, 0)][DBLP]
    Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:140-147 [Conf]
  5. Sunan Tugsinavisut, Youpyo Hong, Daewook Kim, Kyeounsoo Kim, Peter A. Beerel
    Efficient asynchronous bundled-data pipelines for DCT matrix-vector multiplication. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:4, pp:448-461 [Journal]

Search in 0.001secs, Finished in 0.001secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002