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Peter M. Kelly: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Peter M. Kelly, Paul D. Coddington, Andrew L. Wendelborn
    A simplified approach to web service development. [Citation Graph (0, 0)][DBLP]
    ACSW Frontiers, 2006, pp:79-88 [Conf]
  2. P. M. Kelly, T. Martin McGinnity, Liam P. Maguire
    Reducing Interconnection Resource Overhead in Nano-scale FPGAs through MVL Signal Systems. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:282-287 [Conf]
  3. Peter M. Kelly, Paul D. Coddington, Andrew L. Wendelborn
    Compilation of XSLT into Dataflow Graphs for Web Service Composition. [Citation Graph (0, 0)][DBLP]
    CCGRID, 2006, pp:141-149 [Conf]
  4. Peter M. Kelly, Paul D. Coddington, Andrew L. Wendelborn
    Distributed, Parallel Web Service Orchestration Using XSLT. [Citation Graph (0, 0)][DBLP]
    e-Science, 2005, pp:312-319 [Conf]
  5. Fergal Tuffy, Liam McDaid, T. Martin McGinnity, Jose Santos, Peter Kelly, Vunfu Wong Kwan, John Alderman
    A Time Multiplexing Architecture for Inter-neuron Communications. [Citation Graph (0, 0)][DBLP]
    ICANN (1), 2006, pp:944-952 [Conf]
  6. Yajie Chen, Steve Hall, Liam McDaid, Octavian Buiu, Peter Kelly
    A Silicon Synapse Based on a Charge Transfer Device for Spiking Neural Network Application. [Citation Graph (0, 0)][DBLP]
    ISNN (2), 2006, pp:1366-1373 [Conf]
  7. P. M. Kelly, T. Martin McGinnity, Liam P. Maguire, L. M. McDaid
    A Quaternary CLB Design Using Quantum Device Technology on Silicon for FPGA Neural Network Architectures. [Citation Graph (0, 0)][DBLP]
    IWANN, 2005, pp:564-571 [Conf]
  8. P. M. Kelly, C. J. Thompson, T. Martin McGinnity, Liam P. Maguire
    A Binary Multiplier Using RTD Based Threshold Logic Gates. [Citation Graph (0, 0)][DBLP]
    IWANN (2), 2003, pp:41-48 [Conf]

  9. Lambda Calculus as a Workflow Model. [Citation Graph (, )][DBLP]

  10. A Biologically Plausible Neuron Circuit. [Citation Graph (, )][DBLP]

  11. Inter-Neuron Communications for Large-Scale Neural Networks using Capacitive Coupling. [Citation Graph (, )][DBLP]

  12. On the Design of a Low Power Compact Spiking Neuron Cell Based on Charge-Coupled Synapses. [Citation Graph (, )][DBLP]

  13. A programmable facilitating synapse device. [Citation Graph (, )][DBLP]

  14. A Distributed Virtual Machine for Parallel Graph Reduction. [Citation Graph (, )][DBLP]

  15. Analog Spiking Neuron with Charge-Coupled Synapses. [Citation Graph (, )][DBLP]

  16. Reduced Interconnects in Neural Networks Using a Time Multiplexed Architecture Based on Quantum Devices. [Citation Graph (, )][DBLP]

  17. On Two-Layer Hierarchical Networks How Does the Brain Do This? [Citation Graph (, )][DBLP]

  18. Lambda calculus as a workflow model. [Citation Graph (, )][DBLP]

  19. A Solid-State Neuron for Spiking Neural Network Implementation. [Citation Graph (, )][DBLP]

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