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Noppanunt Utamaphethai: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Bryan Black, Brian Mueller, Stephanie Postal, Ryan Rakvic, Noppanunt Utamaphethai, John Paul Shen
    Load Execution Latency Reduction. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1998, pp:29-36 [Conf]
  2. Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen
    Superscalar Processor Validation at the Microarchitecture Level. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:300-305 [Conf]
  3. Noppanunt Utamaphethai, Sumit Ghosh
    Dicaf: A Distributed Architecture for Intelligent Transportation. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1998, v:31, n:3, pp:78-84 [Journal]
  4. Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen
    Effectiveness of Microarchitecture Test Program Generation. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:4, pp:38-49 [Journal]

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