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Miquel Pericàs: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Rubén González, Adrián Cristal, Miquel Pericàs, Mateo Valero, Alexander V. Veidenbaum
    An asymmetric clustered processor based on value content. [Citation Graph (0, 0)][DBLP]
    ICS, 2005, pp:61-70 [Conf]
  2. Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero
    Power-Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2003, pp:113-126 [Conf]
  3. Miquel Pericàs, Rubén González, Adrián Cristal, Alexander V. Veidenbaum, Mateo Valero
    An Optimized Front-End Physical Register File with Banking and Writeback Filtering. [Citation Graph (0, 0)][DBLP]
    PACS, 2004, pp:1-14 [Conf]
  4. Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero
    with Wide Functional Units. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:88-97 [Conf]
  5. Adrián Cristal, Oliverio J. Santana, Francisco J. Cazorla, Marco Galluzzi, Tanausú Ramírez, Miquel Pericàs, Mateo Valero
    Kilo-Instruction Processors: Overcoming the Memory Wall. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2005, v:25, n:3, pp:48-57 [Journal]

  6. A Flexible Heterogeneous Multi-Core Architecture. [Citation Graph (, )][DBLP]

  7. A decoupled KILO-instruction processor. [Citation Graph (, )][DBLP]

  8. A Two-Level Load/Store Queue Based on Execution Locality. [Citation Graph (, )][DBLP]

  9. Chained In-Order/Out-of-Order DoubleCore Architecture. [Citation Graph (, )][DBLP]

  10. Vectorized AES Core for High-throughput Secure Environments. [Citation Graph (, )][DBLP]

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