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W. Robert Daasch: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. William A. Payne III, Fillia Makedon, W. Robert Daasch
    High Speed Interconnection Using the Clos Network. [Citation Graph (0, 0)][DBLP]
    ICS, 1987, pp:96-111 [Conf]
  2. Pan Wu, Rolf Schaumann, W. Robert Daasch
    A 20 MHz Fully-balanced Transconductance-C Filter in 2 µm CMOS Technology. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1188-1191 [Conf]
  3. Haiqiao Xiao, Rolf Schaumann, W. Robert Daasch, Phillip K. Wong, Branimir Pejcinovic
    A radio-frequency CMOS active inductor and its application in designing high-Q filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:197-200 [Conf]
  4. Chee How Lim, W. Robert Daasch, George Cai
    A Thermal-Aware Superscalar Microprocessor (invited). [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:517-522 [Conf]
  5. W. Robert Daasch, Kevin Cota, James McNames, Robert Madge
    Neighbor selection for variance reduction in I_DDQ and other parametric data. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:92-100 [Conf]
  6. W. Robert Daasch, Kevin Cota, James McNames, Robert Madge
    Neighbor Selection for Variance Reduction in IDDQ and Other Parametric Data. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1240- [Conf]
  7. W. Robert Daasch, James McNames, Daniel Bockelman, Kevin Cota
    Variance reduction using wafer patterns in I_ddQ data. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:189-198 [Conf]
  8. W. Robert Daasch, Manu Rehani
    Dude! Where's my data? - Cracking Open the Hermetically Sealed Tester. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1428- [Conf]
  9. Robert Madge, Brady Benware, Ritesh P. Turakhia, W. Robert Daasch, Chris Schuermyer, Jens Ruffler
    In Search of the Optimum Test Set - Adaptive Test Methods for Maximum Defect Coverage and Lowest Test Cost. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:203-212 [Conf]
  10. Robert Madge, B. H. Goh, V. Rajagopalan, C. Macchietto, W. Robert Daasch, Chris Schuermyer, C. Taylor, David Turner
    Screening MinVDD Outliers Using Feed-Forward Voltage Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:673-682 [Conf]
  11. Chris Schuermyer, Brady Benware, Kevin Cota, Robert Madge, W. Robert Daasch, L. Ning
    Screening VDSM Outliers using Nominal and Subthreshold Supply Voltage IDDQ. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:565-573 [Conf]
  12. Chris Schuermyer, Jens Ruffler, W. Robert Daasch
    Minimum Testing Requirements to Screen Temperature Dependent Defects. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:300-308 [Conf]
  13. David Turner, David Abercrombie, James McNames, W. Robert Daasch, Robert Madge
    Isolating and Removing Sources of Variation in Test Data. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:464-471 [Conf]
  14. Ashutosh S. Dhodapkar, Chee How Lim, George Cai, W. Robert Daasch
    TEM2P2EST: A Thermal Enabled Multi-model Power/Performance ESTimator. [Citation Graph (0, 0)][DBLP]
    PACS, 2000, pp:112-125 [Conf]
  15. Brady Benware, Robert Madge, Cam Lu, W. Robert Daasch
    Effectiveness Comparisons of Outlier Screening Methods for Frequency Dependent Defects on Complex ASICs. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:39-46 [Conf]
  16. Ethan Long, W. Robert Daasch, Robert Madge, Brady Benware
    Detection of Temperature Sensitive Defects Using ZTC. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:185-192 [Conf]
  17. Robert Madge, Manu Rehani, Kevin Cota, W. Robert Daasch
    Statistical Post-Processing at Wafersort - An Alternative to Burn-in and a Manufacturable Solution to Test Limit Setting for Sub-micron Technologies. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:69-74 [Conf]
  18. Ritesh P. Turakhia, Brady Benware, Robert Madge, Thaddeus T. Shannon, W. Robert Daasch
    Defect Screening Using Independent Component Analysis on I_DDQ. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:427-432 [Conf]
  19. W. Robert Daasch, James McNames, Robert Madge, Kevin Cota
    Neighborhood Selection for IDDQ Outlier Screening at Wafer Sort. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:5, pp:74-81 [Journal]
  20. Ali Keshavarzi, James Tschanz, Siva Narendra, Vivek De, W. Robert Daasch, Kaushik Roy, Manoj Sachdev, Charles F. Hawkins
    Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:5, pp:36-43 [Journal]
  21. Robert Madge, Brady Benware, W. Robert Daasch
    Obtaining High Defect Coverage for Frequency-Dependent Defects in Complex ASICs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:5, pp:46-53 [Journal]
  22. Ritesh P. Turakhia, W. Robert Daasch, Joel Lurkins, Brady Benware
    Changing Test and Data Modeling Requirements for Screening Latent Defects as Statistical Outliers. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:2, pp:100-109 [Journal]
  23. Michael A. Driscoll, W. Robert Daasch
    Accurate Predictions of Parallel Program Execution Time. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1995, v:25, n:1, pp:16-30 [Journal]

  24. Analyzing the Impact of Fault Tolerant BIST for VLSI Design. [Citation Graph (, )][DBLP]


  25. Statistics in Semiconductor Test: Going beyond Yield. [Citation Graph (, )][DBLP]


  26. Multidimensional Test Escape Rate Modeling. [Citation Graph (, )][DBLP]


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