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Tse-Yu Yeh: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Tse-Yu Yeh, Yale N. Patt
    Two-Level Adaptive Training Branch Prediction. [Citation Graph (1, 0)][DBLP]
    MICRO, 1991, pp:51-61 [Conf]
  2. Tse-Yu Yeh, Deborah T. Marr, Yale N. Patt
    Increasing the Instruction Fetch Rate via Multiple Branch Prediction and a Branch Address Cache. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1993, pp:67-76 [Conf]
  3. Michael Butler, Tse-Yu Yeh, Yale N. Patt, Mitch Alsup, Hunter Scales, Michael Shebanow
    Single Instruction Stream Parallelism is Greater Than Two. [Citation Graph (0, 0)][DBLP]
    ISCA, 1991, pp:276-286 [Conf]
  4. Tse-Yu Yeh, Yale N. Patt
    Alternative Implementations of Two-Level Adaptive Branch Prediction. [Citation Graph (0, 0)][DBLP]
    ISCA, 1992, pp:124-134 [Conf]
  5. Tse-Yu Yeh, Yale N. Patt
    A Comparison of Dynamic Branch Predictors that Use Two Levels of Branch History. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:257-266 [Conf]
  6. Tse-Yu Yeh, Yale N. Patt
    Retrospective: Alternative Implementations of Two-Level Adaptive Training Branch Prediction. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:87-88 [Conf]
  7. Tse-Yu Yeh, Yale N. Patt
    Alternative Implementations of Two-Level Adaptive Branch Prediction. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:451-461 [Conf]
  8. Po-Yung Chang, Eric Hao, Tse-Yu Yeh, Yale N. Patt
    Branch classification: a new mechanism for improving branch predictor performance. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:22-31 [Conf]
  9. Tse-Yu Yeh, Yale N. Patt
    A comprehensive instruction fetch mechanism for a processor supporting speculative execution. [Citation Graph (0, 0)][DBLP]
    MICRO, 1992, pp:129-139 [Conf]
  10. Tse-Yu Yeh, Yale N. Patt
    Branch history table indexing to prevent pipeline bubbles in wide-issue superscalar processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1993, pp:164-175 [Conf]
  11. Tse-Yu Yeh
    Low-Power, High-Performance Architecture of the PWRficient Processor Family. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:2, pp:69-78 [Journal]

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