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Tullio Vardanega :
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Alejandro Alonso , Roberto López , Tullio Vardanega , Juan Antonio de la Puente Using Object Orientation in High Integrity Applications: A Case Study. [Citation Graph (0, 0)][DBLP ] Ada-Europe, 2002, pp:357-366 [Conf ] Matteo Bordin , Tullio Vardanega A New Strategy for the HRT-HOOD to Ada Mapping. [Citation Graph (0, 0)][DBLP ] Ada-Europe, 2005, pp:51-66 [Conf ] José Antonio Pulido , Santiago Urueña , Juan Zamorano , Tullio Vardanega , Juan Antonio de la Puente Hierarchical Scheduling with Ada 2005. [Citation Graph (0, 0)][DBLP ] Ada-Europe, 2006, pp:1-12 [Conf ] Silvia Mazzini , Massimo D'Alessandro , Marco Di Natale , Andrea Domenici , Giuseppe Lipari , Tullio Vardanega HRT-UML: Taking HRT-HOOD onto UML. [Citation Graph (0, 0)][DBLP ] Ada-Europe, 2003, pp:405-416 [Conf ] Tullio Vardanega , Gert Caspersen , Jan Storbank Pedersen A Case Study in the Reuse of On-board Embedded Real-Time Software. [Citation Graph (0, 0)][DBLP ] Ada-Europe, 1999, pp:425-436 [Conf ] Tullio Vardanega , Rodrigo García , Juan Antonio de la Puente An Application Case for Ravenscar Technology: Porting OBOSS to GNAT/ORK. [Citation Graph (0, 0)][DBLP ] Ada-Europe, 2001, pp:392-404 [Conf ] Matteo Bordin , Tullio Vardanega Automated Model-Based Generation of Ravenscar-Compliant Source Code. [Citation Graph (0, 0)][DBLP ] ECRTS, 2005, pp:59-67 [Conf ] Silvia Mazzini , Massimo D'Alessandro , Marco Di Natale , Giuseppe Lipari , Tullio Vardanega Issues in Mapping HRT-HOOD to UML. [Citation Graph (0, 0)][DBLP ] ECRTS, 2003, pp:221-228 [Conf ] Tullio Vardanega , Marco Di Natale , Silvia Mazzini , Massimo D'Alessandro Component-Based Real-Time Design: Mapping HRT-HOOD to UML. [Citation Graph (0, 0)][DBLP ] EUROMICRO, 2004, pp:6-13 [Conf ] Tullio Vardanega , P. David , J.-F. Chane , W. Mader , R. Messaros , Jean Arlat On the Development of Fault-Tolerant On-Board Control Software and its Evaluation by Fault Injection. [Citation Graph (0, 0)][DBLP ] FTCS, 1995, pp:510-515 [Conf ] Tullio Vardanega Experience with the Development of Hard Real-Time Embedded Ada Software. [Citation Graph (0, 0)][DBLP ] ICSE, 1994, pp:301-308 [Conf ] Tullio Vardanega Property-Preserving Reuse-Geared Approach to Model-Driven Development. [Citation Graph (0, 0)][DBLP ] RTCSA, 2006, pp:223-232 [Conf ] Tullio Vardanega Tool support for the construction of statically analysable hard real-time Ada systems. [Citation Graph (0, 0)][DBLP ] IEEE Real-Time Systems Symposium, 1996, pp:129-135 [Conf ] Tullio Vardanega , Jan van Katwijk Productive engineering of predictable embedded real-time systems: the road to maturity. [Citation Graph (0, 0)][DBLP ] Information & Software Technology, 1998, v:40, n:13, pp:745-764 [Journal ] Tullio Vardanega , Juan Zamorano , Juan Antonio de la Puente On the Dynamic Semantics and the Timing Behavior of Ravenscar Kernels. [Citation Graph (0, 0)][DBLP ] Real-Time Systems, 2005, v:29, n:1, pp:59-89 [Journal ] Tullio Vardanega , Gert Caspersen Engineering software reuse for on-board embedded real-time systems. [Citation Graph (0, 0)][DBLP ] Softw., Pract. Exper., 2002, v:32, n:3, pp:233-264 [Journal ] Tullio Vardanega , Jan van Katwijk A Software Process for the Construction of Predictable On-Board Embedded Real-Time Systems. [Citation Graph (0, 0)][DBLP ] Softw., Pract. Exper., 1999, v:29, n:3, pp:235-266 [Journal ] Matteo Bordin , Tullio Vardanega Correctness by Construction for High-Integrity Real-Time Systems: A Metamodel-Driven Approach. [Citation Graph (0, 0)][DBLP ] Ada-Europe, 2007, pp:114-127 [Conf ] Marco Panunzio , Tullio Vardanega A Metamodel-Driven Process Featuring Advanced Model-Based Timing Analysis. [Citation Graph (0, 0)][DBLP ] Ada-Europe, 2007, pp:128-141 [Conf ] Marco Panunzio , Tullio Vardanega An Approach to the Timing Analysis of Hierarchical Systems. [Citation Graph (0, 0)][DBLP ] RTCSA, 2007, pp:157-164 [Conf ] Preservation of Timing Properties with the Ada Ravenscar Profile. [Citation Graph (, )][DBLP ] Cache-Aware Development of High-Integrity Systems. [Citation Graph (, )][DBLP ] Requirements on the Target Programming Language for High-Integrity MDE. [Citation Graph (, )][DBLP ] An MDE methodology for the development of high-integrity real-time systems. [Citation Graph (, )][DBLP ] Fitting Schedulability Analysis Theory into Model-Driven Engineering. [Citation Graph (, )][DBLP ] Property Preservation and Composition with Guarantees: From ASSERT to CHESS. [Citation Graph (, )][DBLP ] On Component-Based Development and High-Integrity Real-Time Systems. [Citation Graph (, )][DBLP ] Real-time Java from an automated code generation perspective. [Citation Graph (, )][DBLP ] Search in 0.003secs, Finished in 0.005secs