The SCEAS System
Navigation Menu
Introduction
Collection Based
Clustering
Ranking
Paper Based
Journals
Conferences
DB Status
Statistics
Search

Search the dblp DataBase

Title:
Author:
Tullio Vardanega: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Alejandro Alonso, Roberto López, Tullio Vardanega, Juan Antonio de la Puente
    Using Object Orientation in High Integrity Applications: A Case Study. [Citation Graph (0, 0)][DBLP]
    Ada-Europe, 2002, pp:357-366 [Conf]
  2. Matteo Bordin, Tullio Vardanega
    A New Strategy for the HRT-HOOD to Ada Mapping. [Citation Graph (0, 0)][DBLP]
    Ada-Europe, 2005, pp:51-66 [Conf]
  3. José Antonio Pulido, Santiago Urueña, Juan Zamorano, Tullio Vardanega, Juan Antonio de la Puente
    Hierarchical Scheduling with Ada 2005. [Citation Graph (0, 0)][DBLP]
    Ada-Europe, 2006, pp:1-12 [Conf]
  4. Silvia Mazzini, Massimo D'Alessandro, Marco Di Natale, Andrea Domenici, Giuseppe Lipari, Tullio Vardanega
    HRT-UML: Taking HRT-HOOD onto UML. [Citation Graph (0, 0)][DBLP]
    Ada-Europe, 2003, pp:405-416 [Conf]
  5. Tullio Vardanega, Gert Caspersen, Jan Storbank Pedersen
    A Case Study in the Reuse of On-board Embedded Real-Time Software. [Citation Graph (0, 0)][DBLP]
    Ada-Europe, 1999, pp:425-436 [Conf]
  6. Tullio Vardanega, Rodrigo García, Juan Antonio de la Puente
    An Application Case for Ravenscar Technology: Porting OBOSS to GNAT/ORK. [Citation Graph (0, 0)][DBLP]
    Ada-Europe, 2001, pp:392-404 [Conf]
  7. Matteo Bordin, Tullio Vardanega
    Automated Model-Based Generation of Ravenscar-Compliant Source Code. [Citation Graph (0, 0)][DBLP]
    ECRTS, 2005, pp:59-67 [Conf]
  8. Silvia Mazzini, Massimo D'Alessandro, Marco Di Natale, Giuseppe Lipari, Tullio Vardanega
    Issues in Mapping HRT-HOOD to UML. [Citation Graph (0, 0)][DBLP]
    ECRTS, 2003, pp:221-228 [Conf]
  9. Tullio Vardanega, Marco Di Natale, Silvia Mazzini, Massimo D'Alessandro
    Component-Based Real-Time Design: Mapping HRT-HOOD to UML. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2004, pp:6-13 [Conf]
  10. Tullio Vardanega, P. David, J.-F. Chane, W. Mader, R. Messaros, Jean Arlat
    On the Development of Fault-Tolerant On-Board Control Software and its Evaluation by Fault Injection. [Citation Graph (0, 0)][DBLP]
    FTCS, 1995, pp:510-515 [Conf]
  11. Tullio Vardanega
    Experience with the Development of Hard Real-Time Embedded Ada Software. [Citation Graph (0, 0)][DBLP]
    ICSE, 1994, pp:301-308 [Conf]
  12. Tullio Vardanega
    Property-Preserving Reuse-Geared Approach to Model-Driven Development. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2006, pp:223-232 [Conf]
  13. Tullio Vardanega
    Tool support for the construction of statically analysable hard real-time Ada systems. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1996, pp:129-135 [Conf]
  14. Tullio Vardanega, Jan van Katwijk
    Productive engineering of predictable embedded real-time systems: the road to maturity. [Citation Graph (0, 0)][DBLP]
    Information & Software Technology, 1998, v:40, n:13, pp:745-764 [Journal]
  15. Tullio Vardanega, Juan Zamorano, Juan Antonio de la Puente
    On the Dynamic Semantics and the Timing Behavior of Ravenscar Kernels. [Citation Graph (0, 0)][DBLP]
    Real-Time Systems, 2005, v:29, n:1, pp:59-89 [Journal]
  16. Tullio Vardanega, Gert Caspersen
    Engineering software reuse for on-board embedded real-time systems. [Citation Graph (0, 0)][DBLP]
    Softw., Pract. Exper., 2002, v:32, n:3, pp:233-264 [Journal]
  17. Tullio Vardanega, Jan van Katwijk
    A Software Process for the Construction of Predictable On-Board Embedded Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    Softw., Pract. Exper., 1999, v:29, n:3, pp:235-266 [Journal]
  18. Matteo Bordin, Tullio Vardanega
    Correctness by Construction for High-Integrity Real-Time Systems: A Metamodel-Driven Approach. [Citation Graph (0, 0)][DBLP]
    Ada-Europe, 2007, pp:114-127 [Conf]
  19. Marco Panunzio, Tullio Vardanega
    A Metamodel-Driven Process Featuring Advanced Model-Based Timing Analysis. [Citation Graph (0, 0)][DBLP]
    Ada-Europe, 2007, pp:128-141 [Conf]
  20. Marco Panunzio, Tullio Vardanega
    An Approach to the Timing Analysis of Hierarchical Systems. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2007, pp:157-164 [Conf]

  21. Preservation of Timing Properties with the Ada Ravenscar Profile. [Citation Graph (, )][DBLP]


  22. Cache-Aware Development of High-Integrity Systems. [Citation Graph (, )][DBLP]


  23. Requirements on the Target Programming Language for High-Integrity MDE. [Citation Graph (, )][DBLP]


  24. An MDE methodology for the development of high-integrity real-time systems. [Citation Graph (, )][DBLP]


  25. Fitting Schedulability Analysis Theory into Model-Driven Engineering. [Citation Graph (, )][DBLP]


  26. Property Preservation and Composition with Guarantees: From ASSERT to CHESS. [Citation Graph (, )][DBLP]


  27. On Component-Based Development and High-Integrity Real-Time Systems. [Citation Graph (, )][DBLP]


  28. Real-time Java from an automated code generation perspective. [Citation Graph (, )][DBLP]


Search in 0.047secs, Finished in 0.050secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
Introduction Collection Based Clustering Ranking Paper Based Journals Conferences DB Status Statistics Search
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002