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William Fornaciari: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. William Fornaciari, Donatella Sciuto
    HW/SW Co-design of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    Ada-Europe, 1999, pp:344-355 [Conf]
  2. Luca Negri, Domenico Barretta, William Fornaciari
    Application-level power management in pervasive computing systems: a case study. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2004, pp:78-88 [Conf]
  3. Alberto Allara, S. Filipponi, Fabio Salice, William Fornaciari, Donatella Sciuto
    A Flexible Model for Evaluating the Behavior of Hardware/Software Systems. [Citation Graph (0, 0)][DBLP]
    CODES, 1997, pp:109-114 [Conf]
  4. Stefano Antoniazzi, Alessandro Balboni, William Fornaciari, Donatella Sciuto
    A methodology for control-dominated systems codesign. [Citation Graph (0, 0)][DBLP]
    CODES, 1994, pp:2-9 [Conf]
  5. Alessandro Balboni, William Fornaciari, Donatella Sciuto
    Partitioning and Exploration Strategies in the TOSCA Co-Design Flow. [Citation Graph (0, 0)][DBLP]
    CODES, 1996, pp:62-69 [Conf]
  6. William Fornaciari, M. Polentarutti, Donatella Sciuto, Cristina Silvano
    Power optimization of system-level address buses based on software profiling. [Citation Graph (0, 0)][DBLP]
    CODES, 2000, pp:29-33 [Conf]
  7. Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto
    Energy estimation for 32-bit microprocessors. [Citation Graph (0, 0)][DBLP]
    CODES, 2000, pp:24-28 [Conf]
  8. Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto
    Source-level execution time estimation of C programs. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:98-103 [Conf]
  9. William Fornaciari, Fabio Salice, Umberto Bondi, Edi Magini
    Development cost and size estimation starting from high-level specifications. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:86-91 [Conf]
  10. William Fornaciari, Fabio Salice, Daniele Paolo Scarpazza
    Early estimation of the size of VHDL projects. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:207-212 [Conf]
  11. William Fornaciari, Donatella Sciuto, Cristina Silvano
    Power estimation for architectural exploration of HW/SW communication on system-level buses. [Citation Graph (0, 0)][DBLP]
    CODES, 1999, pp:152-156 [Conf]
  12. William Fornaciari, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria
    A design framework to efficiently explore energy-delay tradeoffs. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:260-265 [Conf]
  13. Donatella Sciuto, Fabio Salice, Luigi Pomante, William Fornaciari
    Metrics for design space exploration of heterogeneous multiprocessor embedded systems. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:55-60 [Conf]
  14. Carlo Brandolese, William Fornaciari, Fabio Salice
    An area estimation methodology for FPGA based designs at systemc-level. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:129-132 [Conf]
  15. Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto
    An instruction-level functionally-based energy estimation model for 32-bits microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:346-351 [Conf]
  16. Domenico Barretta, William Fornaciari, Mariagiovanna Sami, Daniele Bagni
    Multithreaded Extension to Multicluster VLIW Processors for Embedded Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:748-749 [Conf]
  17. Cesare Alippi, William Fornaciari, Laura Pozzi, Mariagiovanna Sami
    A DAG-Based Design Approach for Reconfigurable VLIW Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:778-779 [Conf]
  18. Alberto Allara, William Fornaciari, Fabio Salice, Donatella Sciuto
    A Model for System-Level Timed Analysis and Profiling. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:204-210 [Conf]
  19. Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto
    Library Functions Timing Characterization for Source-Level Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11132-11133 [Conf]
  20. Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto
    Analysis and Modeling of Energy Reducing Source Code Transformations. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:306-311 [Conf]
  21. William Fornaciari, P. Micheli, Fabio Salice, L. Zampella
    A First Step Towards Hw/Sw Partitioning of UML Specifications. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10668-10673 [Conf]
  22. William Fornaciari, Donatella Sciuto, Cristina Silvano
    Influence of Caching and Encoding on Power Dissipation of System-Level Buses for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:762-763 [Conf]
  23. Cesare Alippi, William Fornaciari, Laura Pozzi, Mariagiovanna Sami
    Determining the optimum extended instruction-set architecture for application specific reconfigurable VLIW CPUs (poster abstract). [Citation Graph (0, 0)][DBLP]
    FPGA, 2000, pp:218- [Conf]
  24. William Fornaciari, Vincenzo Piuri, Luigi Ripamonti
    Virtualization of FPGA via segmentation (poster abstract). [Citation Graph (0, 0)][DBLP]
    FPGA, 2000, pp:222- [Conf]
  25. Giovanni Beltrame, Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto, Vito Trianni
    An Assembly-Level Execution-Time Model for Pipelined Architectures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:195-200 [Conf]
  26. Domenico Barretta, William Fornaciari, Mariagiovanna Sami, Danilo Pau
    SIMD Extension to VLIW Multicluster Processors for Embedded Applications. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:523-526 [Conf]
  27. Alberto Allara, S. Filipponi, William Fornaciari, Fabio Salice, Donatella Sciuto
    Improving Design Turnaround Time via Two-Levels Hw/Sw Co-Simulation. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:400-405 [Conf]
  28. Stefano Antoniazzi, Alessandro Balboni, William Fornaciari, Donatella Sciuto
    HW/SW Codesign for Embedded Telecom Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:278-281 [Conf]
  29. William Fornaciari, Donatella Sciuto, Cristina Silvano
    Power Estimation of System-Level Buses for Microprocessor-Based Architectures: A Case Study. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:131-0 [Conf]
  30. William Fornaciari, Vincenzo Piuri
    Virtual FPGAs: Some Steps Behind the Physical Barriers. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP Workshops, 1998, pp:7-12 [Conf]
  31. William Fornaciari, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria
    Fast system-level exploration of memory architectures driven by energy-delay metrics. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:502-505 [Conf]
  32. William Fornaciari, Vito Trianni, Carlo Brandolese, Donatella Sciuto, Fabio Salice, Giovanni Beltrame
    Modeling Assembly Instruction Timing in Superscalar Architectures. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:132-137 [Conf]
  33. Alessandro Balboni, William Fornaciari, M. Vincenzi, Donatella Sciuto
    The Use of a Virtual Instruction Set for the Software Synthesis of HW/SW Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:77-82 [Conf]
  34. Giovanni Beltrame, Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto, Vito Trianni
    Dynamic modeling of inter-instruction effects for execution time estimation. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:136-141 [Conf]
  35. Cristiana Bolchini, William Fornaciari, Fabio Salice, Donatella Sciuto
    Concurrent Error Detection at Architectural Level. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:72-75 [Conf]
  36. Carlo Brandolese, William Fornaciari, Luigi Pomante, Fabio Salice, Donatella Sciuto
    A Multi-Level Strategy for Software Power Estimation. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:187-192 [Conf]
  37. William Fornaciari, Vincenzo Piuri, Andrea Prestileo, Vittorio Zaccaria
    An Agent-Based Approach to Full Interoperability and Allocation Transparency in Distributed File Systems. [Citation Graph (0, 0)][DBLP]
    MATA, 2001, pp:153-162 [Conf]
  38. Carlo Brandolese, William Fornaciari, Fabio Salice
    Discrete-Event Modeling and Simulation of Superscalar Microprocessor Architectures. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:238-247 [Conf]
  39. Cesare Alippi, William Fornaciari, Laura Pozzi, Mariagiovanna Sami
    Determining the Optimum Extended Instruction-Set Architecture for Application Specific Reconfigurable VLIW CPUs. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2001, pp:50-57 [Conf]
  40. Fabio Salice, William Fornaciari, Luca Del Vecchio, Luigi Pomante
    Partitioning of Embedded Applications onto Heterogeneous Multiprocessor Architectures. [Citation Graph (0, 0)][DBLP]
    SAC, 2003, pp:661-665 [Conf]
  41. William Fornaciari, Donatella Sciuto
    A Two-Level Cosimulation Environment. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1997, v:30, n:6, pp:109-111 [Journal]
  42. Alberto Allara, Massimo Bombana, William Fornaciari, Fabio Salice
    A Case Study in Design Space Exploration: The Tosca Environment Applied to a Telecommunication Link Controller. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:2, pp:60-72 [Journal]
  43. Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto
    The Impact of Source Code Transformations on Software Power and Energy Consumption. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2002, v:11, n:5, pp:477-502 [Journal]
  44. Carlo Brandolese, William Fornaciari, Luigi Pomante, Fabio Salice, Donatella Sciuto
    Affinity-Driven System Design Exploration for Heterogeneous Multiprocessor SoC. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:5, pp:508-519 [Journal]
  45. Carlo Brandolese, Fabio Salice, William Fornaciari, Donatella Sciuto
    Static power modeling of 32-bit microprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:11, pp:1306-1316 [Journal]
  46. William Fornaciari, Fabio Salice
    A new architecture for the automatic design of custom digital neural network. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:4, pp:502-506 [Journal]
  47. William Fornaciari, P. Gubian, Donatella Sciuto, Cristina Silvano
    Power estimation of embedded systems: a hardware/software codesign approach. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:2, pp:266-275 [Journal]

  48. A Hierarchical Distributed Control for Power and Performances Optimization of Embedded Systems. [Citation Graph (, )][DBLP]


  49. Predictive models for multimedia applications power consumption based on use-case and OS level analysis. [Citation Graph (, )][DBLP]


  50. Constrained Power Management: Application to a multimedia mobile platform. [Citation Graph (, )][DBLP]


  51. Measurement, Analysis and Modeling of RTOS System Calls Timing. [Citation Graph (, )][DBLP]


  52. Models and Tradeoffs in WSN System-Level Design. [Citation Graph (, )][DBLP]


  53. A Framework for Compile-time and Run-time Management of Non-functional Aspects in WSNs Nodes. [Citation Graph (, )][DBLP]


  54. The role of VHDL within the TOSCA hardware/software codesign framework. [Citation Graph (, )][DBLP]


  55. An Internal Representation Model for System-Level Co-Design of Heterogeneous Multiprocessor Embedded System. [Citation Graph (, )][DBLP]


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