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Donatella Sciuto: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. William Fornaciari, Donatella Sciuto
    HW/SW Co-design of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    Ada-Europe, 1999, pp:344-355 [Conf]
  2. Roberto Cordone, Fabrizio Ferrandi, Marco D. Santambrogio, Gianluca Palermo, Donatella Sciuto
    Using speculative computation and parallelizing techniques to improve scheduling of control based designs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:898-904 [Conf]
  3. Giovanni Beltrame, Gianluca Palermo, Donatella Sciuto, Cristina Silvano
    Plug-in of power models in the StepNP exploration platform: analysis of power/performance trade-offs. [Citation Graph (0, 0)][DBLP]
    CASES, 2004, pp:85-92 [Conf]
  4. Alberto Allara, S. Filipponi, Fabio Salice, William Fornaciari, Donatella Sciuto
    A Flexible Model for Evaluating the Behavior of Hardware/Software Systems. [Citation Graph (0, 0)][DBLP]
    CODES, 1997, pp:109-114 [Conf]
  5. Stefano Antoniazzi, Alessandro Balboni, William Fornaciari, Donatella Sciuto
    A methodology for control-dominated systems codesign. [Citation Graph (0, 0)][DBLP]
    CODES, 1994, pp:2-9 [Conf]
  6. Alessandro Balboni, William Fornaciari, Donatella Sciuto
    Partitioning and Exploration Strategies in the TOSCA Co-Design Flow. [Citation Graph (0, 0)][DBLP]
    CODES, 1996, pp:62-69 [Conf]
  7. William Fornaciari, M. Polentarutti, Donatella Sciuto, Cristina Silvano
    Power optimization of system-level address buses based on software profiling. [Citation Graph (0, 0)][DBLP]
    CODES, 2000, pp:29-33 [Conf]
  8. Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto
    Energy estimation for 32-bit microprocessors. [Citation Graph (0, 0)][DBLP]
    CODES, 2000, pp:24-28 [Conf]
  9. Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto
    Source-level execution time estimation of C programs. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:98-103 [Conf]
  10. William Fornaciari, Donatella Sciuto, Cristina Silvano
    Power estimation for architectural exploration of HW/SW communication on system-level buses. [Citation Graph (0, 0)][DBLP]
    CODES, 1999, pp:152-156 [Conf]
  11. William Fornaciari, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria
    A design framework to efficiently explore energy-delay tradeoffs. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:260-265 [Conf]
  12. Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria
    Instruction-level power estimation for embedded VLIW cores. [Citation Graph (0, 0)][DBLP]
    CODES, 2000, pp:34-38 [Conf]
  13. Donatella Sciuto, Fabio Salice, Luigi Pomante, William Fornaciari
    Metrics for design space exploration of heterogeneous multiprocessor embedded systems. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:55-60 [Conf]
  14. Giovanni Beltrame, Dario Bruschi, Donatella Sciuto, Cristina Silvano
    Decision-theoretic exploration of multiProcessor platforms. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:205-210 [Conf]
  15. Giovanni Agosta, Francesco Bruschi, Donatella Sciuto
    Static analysis of transaction-level models. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:448-453 [Conf]
  16. Andrea Bona, Mariagiovanna Sami, Donatella Sciuto, Vittorio Zaccaria, Cristina Silvano, Roberto Zafalon
    Energy estimation and optimization of embedded VLIW processors based on instruction clustering. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:886-891 [Conf]
  17. Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto
    An instruction-level functionally-based energy estimation model for 32-bits microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:346-351 [Conf]
  18. Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino, Donatella Sciuto
    Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:467-470 [Conf]
  19. Alberto Allara, William Fornaciari, Fabio Salice, Donatella Sciuto
    A Model for System-Level Timed Analysis and Profiling. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:204-210 [Conf]
  20. Giovanni Beltrame, Donatella Sciuto, Cristina Silvano, Damien Lyonnard, Chuck Pilkington
    Exploiting TLM and object introspection for system-level simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:100-105 [Conf]
  21. Luca Benini, Giovanni De Micheli, Donatella Sciuto, Enrico Macii, Cristina Silvano
    Address Bus Encoding Techniques for System-Level Power Optimization. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:861-0 [Conf]
  22. Francesco Bruschi, Michele Chiamenti, Fabrizio Ferrandi, Donatella Sciuto
    Error Simulation Based on the SystemC Design Description Language. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1135- [Conf]
  23. Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto
    Library Functions Timing Characterization for Source-Level Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11132-11133 [Conf]
  24. Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto
    Analysis and Modeling of Energy Reducing Source Code Transformations. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:306-311 [Conf]
  25. Cristiana Bolchini, Fabio Salice, Donatella Sciuto
    Fault Analysis in Networks with Concurrent Error Detection Properties. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:957-958 [Conf]
  26. Cristiana Bolchini, Fabio Salice, Donatella Sciuto, Luigi Pomante
    Reliable System Specification for Self-Checking Data-Paths. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1278-1283 [Conf]
  27. Andrea Bona, Mariagiovanna Sami, Donatella Sciuto, Vittorio Zaccaria, Cristina Silvano, Roberto Zafalon
    An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW Cores. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1128- [Conf]
  28. Roberto Cordone, Fabrizio Ferrandi, Donatella Sciuto, Roberto Wolfler Calvo
    An Efficient Heuristic Approach to Solve the Unate Covering Problem. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:364-371 [Conf]
  29. Fabrizio Ferrandi, Franco Fummi, Luca Gerli, Donatella Sciuto
    Symbolic Functional Vector Generation for VHDL Specifications. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:442-0 [Conf]
  30. Fabrizio Ferrandi, G. Ferrara, Donatella Sciuto, Alessandro Fin, Franco Fummi
    Functional test generation for behaviorally sequential models. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:403-410 [Conf]
  31. Fabrizio Ferrandi, Michele Rendine, Donatella Sciuto
    Functional Verification for SystemC Descriptions Using Constraint Solving. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:744-751 [Conf]
  32. William Fornaciari, Donatella Sciuto, Cristina Silvano
    Influence of Caching and Encoding on Power Dissipation of System-Level Buses for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:762-763 [Conf]
  33. Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon
    Exploiting data forwarding to reduce the power budget of VLIW embedded processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:252-257 [Conf]
  34. Heinz-Joseph Schlebusch, Gary Smith, Donatella Sciuto, Daniel Gajski, Carsten Mielenz, Christopher K. Lennard, Frank Ghenassia, Stuart Swan, Joachim Kunkel
    Transaction Based Design: Another Buzzword or the Solution to a Design Problem? [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10876-10879 [Conf]
  35. Donatella Sciuto, Grant Martin, Wolfgang Rosenstiel, Stuart Swan, Frank Ghenassia, Peter Flake, Johny Srouji
    SystemC and SystemVerilog: Where do They Fit? Where are They Going? [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:122-129 [Conf]
  36. Giampaolo Agosta, Francesco Bruschi, Donatella Sciuto
    Synthesis of Dynamic Class Loading Specifications on Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    DELTA, 2004, pp:431-433 [Conf]
  37. Fabrizio Ferrandi, Pier Luca Lanzi, Donatella Sciuto, Mara Tanelli
    System-level metrics for hardware/software architectural mapping. [Citation Graph (0, 0)][DBLP]
    DELTA, 2004, pp:231-236 [Conf]
  38. Marco Brera, Fabrizio Ferrandi, Donatella Sciuto, Franco Fummi
    Increase the Behavioral Fault Model Accuracy Using High-Level Synthesis Information. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:174-180 [Conf]
  39. Giacomo Buonanno, Franco Fummi, Donatella Sciuto
    Fault Detection in Sequential Circuits through Functional Testing. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:191-198 [Conf]
  40. Cristiana Bolchini, Giacomo Buonanno, M. Cozzini, Donatella Sciuto, Renato Stefanelli
    Designing Ad-Hoc Codes for the Realization of Fault Tolerant CMOS Networks. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:204-211 [Conf]
  41. Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli
    A CMOS Fault Tolerant Architecture for Swith-Level Faults. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:10-18 [Conf]
  42. Cristiana Bolchini, Antonio Miele, Fabio Salice, Donatella Sciuto
    A model of soft error effects in generic IP processors. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:334-342 [Conf]
  43. Cristiana Bolchini, Antonio Miele, Fabio Salice, Donatella Sciuto, Luigi Pomante
    Reliable System Co-Design: The FIR Case Study. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:433-441 [Conf]
  44. Cristiana Bolchini, Luigi Pomante, Donatella Sciuto, Fabio Salice
    A Synthesis Methodology Aimed at Improving the Quality of TSC Devices. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:247-255 [Conf]
  45. Cristiana Bolchini, Fabio Salice, Donatella Sciuto
    Designing Self-Checking FPGAs through Error Detection Codes. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:60-68 [Conf]
  46. Cristiana Bolchini, Donatella Sciuto, Fabio Salice
    Designing Networks with Error Detection Properties through the Fault-Error Relation. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:290-297 [Conf]
  47. Cristiana Bolchini, Fabio Salice, Donatella Sciuto, R. Zavaglia
    An Integrated Design Approach for Self-Checking FPGAs. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:443-450 [Conf]
  48. Massimo Bombana, Giacomo Buonanno, Patrizia Cavalloro, Fabrizio Ferrandi, Donatella Sciuto, Giuseppe Zaza
    Reduction of Fault Detection Costs through Testable Design of Sequential Architectures with Signal Feedbacks. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:223-230 [Conf]
  49. G. Biasoli, Fabrizio Ferrandi, Donatella Sciuto, Alessandro Fin, Franco Fummi
    BIST Architectures Selection Based on Behavioral Testing. [Citation Graph (0, 0)][DBLP]
    DFT, 2000, pp:292-298 [Conf]
  50. Franco Fummi, Donatella Sciuto, Micaela Serra
    Test Generation for Stuck-at and Gate-Delay Faults in Sequential Circuits: A Mixed Functional/Structural Method. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:254-262 [Conf]
  51. Fabio Salice, Mariagiovanna Sami, Donatella Sciuto
    Synthesis of Multi-level Self-Checking Logic. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:115-123 [Conf]
  52. Donatella Sciuto, Cristina Silvano, Renato Stefanelli
    Systematic AUED Codes for Self-Checking Architectures. [Citation Graph (0, 0)][DBLP]
    DFT, 1998, pp:183-191 [Conf]
  53. Maurizio Rebaudengo, Luca Sterpone, Massimo Violante, Cristiana Bolchini, Antonio Miele, Donatella Sciuto
    Combined software and hardware techniques for the design of reliable IP processors. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:265-273 [Conf]
  54. Giovanni Agosta, Francesco Bruschi, Marco D. Santambrogio, Donatella Sciuto
    Synthesis of Object Oriented Models on Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:249-250 [Conf]
  55. Carlo Amicucci, Fabrizio Ferrandi, Marco D. Santambrogio, Donatella Sciuto
    SyCERS: a SystemC Design Exploration Framework for SoC Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:63-69 [Conf]
  56. Giovanni Agosta, Francesco Bruschi, Marco D. Santambrogio, Donatella Sciuto
    A Data Oriented Approach to the Design of Reconfigurable Stream Decoders. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2005, pp:107-112 [Conf]
  57. Alessandro Balboni, Claudio Costi, Franco Fummi, Donatella Sciuto
    From Behavioral Description to Systolic Array Based Architectures. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:657- [Conf]
  58. Franco Fummi, Donatella Sciuto, Micaela Serra
    A Functional Approach to Delay Faults Test Generation for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:51-57 [Conf]
  59. Alberto Donato, Fabrizio Ferrandi, Massimo Redaelli, Marco D. Santambrogio, Donatella Sciuto
    Caronte: A Complete Methodology for the Implementation of Partially Dynamically Self-Reconfiguring Systems on FPGA Platforms. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:321-322 [Conf]
  60. Fabrizio Ferrandi, Pier Luca Lanzi, Donatella Sciuto
    System Level Hardware-Software Design Exploration with XCS. [Citation Graph (0, 0)][DBLP]
    GECCO (2), 2004, pp:763-773 [Conf]
  61. F. S. Bietti, Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto
    VHDL Testability Analysis Based on Fault Clustering and Implicit Fault Injection. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:237-242 [Conf]
  62. Cristiana Bolchini, Fabio Salice, Donatella Sciuto
    Parity Bit Code: Achieving a Complete Fault Coverage in the Design of TSC Combinational Networks. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1997, pp:32-0 [Conf]
  63. Luca Benini, Giovanni De Micheli, Enrico Macii, Donatella Sciuto, Cristina Silvano
    Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1997, pp:77-82 [Conf]
  64. Giacomo Buonanno, Fabrizio Ferrandi, L. Ferrandi, Franco Fummi, Donatella Sciuto
    How an "Evolving" Fault Model Improves the Behavioral Test Generation. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1997, pp:124-0 [Conf]
  65. Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino, Donatella Sciuto
    Test Generation for Networks of Interacting FSMs Using Symbolic Techniques. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:208-213 [Conf]
  66. Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
    A design kit for a fully working shared memory multiprocessor on FPGA. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:219-222 [Conf]
  67. Giovanni Agosta, Francesco Bruschi, Donatella Sciuto
    An efficient cost-based canonical form for Boolean matching. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:445-448 [Conf]
  68. Giovanni Beltrame, Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto, Vito Trianni
    An Assembly-Level Execution-Time Model for Pipelined Architectures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:195-200 [Conf]
  69. Peter Koo, Fabrizio Lombardi, Donatella Sciuto
    A Routing Algorithm for Harvesting Multipipeline Arrays with Small Intercell and Pipeline Delays. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:2-5 [Conf]
  70. Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria
    Power Exploration for Embedded VLIW Architectures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:498-503 [Conf]
  71. Cristiana Bolchini, Donatella Sciuto, Fabio Salice
    A TSC Evaluation Function for Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:555-560 [Conf]
  72. M. Bacis, Giacomo Buonanno, Fabrizio Ferrandi, Franco Fummi, Luca Gerli, Donatella Sciuto
    Application of a Testing Framework to VHDL Descriptions at Different Abstraction Levels. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:654-658 [Conf]
  73. Alberto Allara, S. Filipponi, William Fornaciari, Fabio Salice, Donatella Sciuto
    Improving Design Turnaround Time via Two-Levels Hw/Sw Co-Simulation. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:400-405 [Conf]
  74. Stefano Antoniazzi, Alessandro Balboni, William Fornaciari, Donatella Sciuto
    HW/SW Codesign for Embedded Telecom Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:278-281 [Conf]
  75. Giacomo Buonanno, Franco Fummi, Donatella Sciuto
    Functional Fault Models and Gate Level Coverage for Sequential Architectures. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:572-575 [Conf]
  76. Franco Fummi, Donatella Sciuto, M. Serro
    Synthesis for testability of large complexity controllers. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:180-0 [Conf]
  77. William Fornaciari, Donatella Sciuto, Cristina Silvano
    Power Estimation of System-Level Buses for Microprocessor-Based Architectures: A Case Study. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:131-0 [Conf]
  78. Fabrizio Ferrandi, Donatella Sciuto, Alessandro Fin, Franco Fummi
    An Application of Genetic Algorithms and BDDs to Functional Testing. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:48-0 [Conf]
  79. Paolo Faverio, Donatella Sciuto, Giacomo Buonanno
    Using Critical Success Factors for Assessing Critical Activities in ERP Implementation within SMEs. [Citation Graph (0, 0)][DBLP]
    ICEIS (1), 2005, pp:285-292 [Conf]
  80. Francesco Bruschi, Paolo Faverio, R. Hodges, L. Mari, D. Restelli, Donatella Sciuto
    Virtual Community in the Classroom: An Innovating Tool for Elearning. [Citation Graph (0, 0)][DBLP]
    EDUTECH, 2004, pp:123-132 [Conf]
  81. Cristiana Bolchini, Luigi Pomante, Fabio Salice, Donatella Sciuto
    Reliability Properties Assessment at System Level: A Co-design Framework. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:165-171 [Conf]
  82. Cristiana Bolchini, Luigi Pomante, Fabio Salice, Donatella Sciuto
    A System Level Approach in Designing Dual-Duplex Fault Tolerant Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:32-0 [Conf]
  83. Cristiana Bolchini, Fabio Salice, Donatella Sciuto
    Designing Reliable Embedded Systems Based on 32 Bit Microprocessors. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:137- [Conf]
  84. Fabrizio Ferrandi, Marco D. Santambrogio, Donatella Sciuto
    A Design Methodology for Dynamic Reconfiguration: The Caronte Architecture. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  85. Giacomo Buonanno, Stefano Gramignoli, Aurelio Ravarini, Marco Tagliavini, Donatella Sciuto
    ICT diffusion and strategic role within Italian SMEs. [Citation Graph (0, 0)][DBLP]
    IRMA Conference, 2000, pp:373-378 [Conf]
  86. Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli
    CMOS Reliability Improvements Through a New Fault Tolerant Technique. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:83-86 [Conf]
  87. Cristiana Bolchini, Franco Fummi, Donatella Sciuto
    Two-Dimensional Sequential Array Architectures: Design for Testability Approaches. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:81-84 [Conf]
  88. Cristiana Bolchini, Donatella Sciuto
    An Output/State Encoding for Self-Checking Finite State Machine. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:2136-2139 [Conf]
  89. Giacomo Buonanno, Fabio Salice, Donatella Sciuto
    Behavior of Self-Checking Checkers for 1-out-of-3 Codes Based on Pass-Transistor Logic. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1924-1927 [Conf]
  90. Giacomo Buonanno, Franco Fummi, Donatella Sciuto
    Functional Testing and Constrained Synthesis of Sequential Architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1523-1526 [Conf]
  91. Giacomo Buonanno, Fabrizio Ferrandi, Donatella Sciuto
    Data Path Testability Analysis Based on BDDs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:2012-2014 [Conf]
  92. Luca Penzo, Donatella Sciuto, Cristina Silvano
    GECO: A Tool for Automatic Generation of Error Control Codes for Computer Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:912-915 [Conf]
  93. Margherita Pillan, Donatella Sciuto
    Constraint Generation & Placement for Automatic Layout Design of Analog Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:355-358 [Conf]
  94. William Fornaciari, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria
    Fast system-level exploration of memory architectures driven by energy-delay metrics. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:502-505 [Conf]
  95. William Fornaciari, Vito Trianni, Carlo Brandolese, Donatella Sciuto, Fabio Salice, Giovanni Beltrame
    Modeling Assembly Instruction Timing in Superscalar Architectures. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:132-137 [Conf]
  96. Alessandro Balboni, William Fornaciari, M. Vincenzi, Donatella Sciuto
    The Use of a Virtual Instruction Set for the Software Synthesis of HW/SW Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:77-82 [Conf]
  97. Giovanni Beltrame, Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto, Vito Trianni
    Dynamic modeling of inter-instruction effects for execution time estimation. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:136-141 [Conf]
  98. Cristiana Bolchini, William Fornaciari, Fabio Salice, Donatella Sciuto
    Concurrent Error Detection at Architectural Level. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:72-75 [Conf]
  99. Cristiana Bolchini, Luigi Pomante, Fabio Salice, Donatella Sciuto
    On-line fault detection in a hardware/software co-design environment. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:51-56 [Conf]
  100. Carlo Brandolese, William Fornaciari, Luigi Pomante, Fabio Salice, Donatella Sciuto
    A Multi-Level Strategy for Software Power Estimation. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:187-192 [Conf]
  101. Angelo P. E. Rosiello, Fabrizio Ferrandi, Davide Pandini, Donatella Sciuto
    A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:92-97 [Conf]
  102. Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
    A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:331-336 [Conf]
  103. Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
    An Internal Partial Dynamic Reconfiguration Implementation of the JPEG Encoder for Low-Cost FPGAsb. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:449-450 [Conf]
  104. S. Corbetta, Fabrizio Ferrandi, M. Morandi, M. Novati, Marco D. Santambrogio, Donatella Sciuto
    Two Novel Approaches to Online Partial Bitstream Relocation in a Dynamically Reconfigurable System. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:457-458 [Conf]
  105. Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto
    Implicit test generation for behavioral VHDL models. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:587-0 [Conf]
  106. Tiziana Gravagnoli, Fabrizio Ferrandi, Pier Luca Lanzi, Donatella Sciuto
    Automatic Test Pattern Generation with BOA. [Citation Graph (0, 0)][DBLP]
    PPSN, 2006, pp:423-432 [Conf]
  107. X. Sun, Yinan N. Shen, Fabrizio Lombardi, Donatella Sciuto
    Protocol Conformance Testing by Discriminating UIO Sequences. [Citation Graph (0, 0)][DBLP]
    PSTV, 1991, pp:349-364 [Conf]
  108. Fabrizio Lombardi, Donatella Sciuto, Renato Stefanelli
    A Technique for Reconfiguring Two Dimensional VLSI Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1987, pp:44-53 [Conf]
  109. Lorenzo Salvemini, Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon
    A Methodology for the Efficient Architectural Exploration of Energy-Delay Trade-offs for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    SAC, 2003, pp:672-678 [Conf]
  110. Massimo Bombana, Giacomo Buonanno, Patrizia Cavalloro, Fabrizio Ferrandi, Donatella Sciuto, Giuseppe Zaza
    An Expert Solution to Functional Testability Analysis of VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    SEKE, 1993, pp:263-265 [Conf]
  111. Yinan N. Shen, Fabrizio Lombardi, Donatella Sciuto
    Evaluation and improvement of fault coverage for verification and validation of protocols. [Citation Graph (0, 0)][DBLP]
    SPDP, 1990, pp:200-207 [Conf]
  112. Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli
    A new switching-level approach to multiple-output functions synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:125-129 [Conf]
  113. Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli
    New CMOS Structures for the Synthesis of Dominant Functions. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:367-370 [Conf]
  114. Luca Penzo, Donatella Sciuto, Cristina Silvano
    VLSI design of systematic odd-weight-column byte error detecting SEC-DED codes. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:156-160 [Conf]
  115. Fabrizio Ferrandi, G. Fornara, Donatella Sciuto, G. Ferrara, Franco Fummi
    Testability Alternatives Exploration through Functional Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:423-430 [Conf]
  116. Franco Fummi, Donatella Sciuto
    Implicit test pattern generation constrained to cellular automata embedding. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:54-59 [Conf]
  117. William Fornaciari, Donatella Sciuto
    A Two-Level Cosimulation Environment. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1997, v:30, n:6, pp:109-111 [Journal]
  118. Cristiana Bolchini, Fabio Salice, Donatella Sciuto
    Fault Analysis for Networks with Concurrent Error Detection. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:4, pp:66-74 [Journal]
  119. Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto, Enrico Macii, Massimo Poncino
    Testing Core-Based Systems: A Symbolic Methodology. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:4, pp:69-77 [Journal]
  120. Donatella Sciuto
    Guest Editor's Introduction: Design Tools for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:2, pp:11-13 [Journal]
  121. Francesco Bruschi, Fabrizio Ferrandi, Donatella Sciuto
    A Framework for the Functional Verification of SystemC Models. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2005, v:33, n:6, pp:667-695 [Journal]
  122. Franco Fummi, Donatella Sciuto
    A complete testing strategy based on interacting and hierarchical FSMs. [Citation Graph (0, 0)][DBLP]
    Integration, 1997, v:23, n:1, pp:75-93 [Journal]
  123. Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto
    The Impact of Source Code Transformations on Software Power and Energy Consumption. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2002, v:11, n:5, pp:477-502 [Journal]
  124. Fabiano Cattaneo, Alfonso Fuggetta, Donatella Sciuto
    Pursuing coherence in software process assessment and improvement. [Citation Graph (0, 0)][DBLP]
    Software Process: Improvement and Practice, 2001, v:6, n:1, pp:3-22 [Journal]
  125. Carlo Brandolese, William Fornaciari, Luigi Pomante, Fabio Salice, Donatella Sciuto
    Affinity-Driven System Design Exploration for Heterogeneous Multiprocessor SoC. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:5, pp:508-519 [Journal]
  126. Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli
    Innovative Structures for CMOS Combinational Gates Synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:4, pp:385-399 [Journal]
  127. Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto
    Test Generation and Testability Alternatives Exploration of Critical Algorithms for Embedded Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:2, pp:200-215 [Journal]
  128. Franco Fummi, Donatella Sciuto
    A Hierarchical Test Generation Approach for Large Controllers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:4, pp:289-302 [Journal]
  129. Franco Fummi, Donatella Sciuto, Micaela Serra
    Synthesis for Testability of Highly Complex Controllers by Functional Redundancy Removal. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:12, pp:1305-1323 [Journal]
  130. Donatella Sciuto, Fabrizio Lombardi
    On Functional Testing of Array Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:11, pp:1480-1484 [Journal]
  131. Alessandro Balboni, Claudio Costi, Massimo Pellencin, Andrea Quadrini, Donatella Sciuto
    Clock skew reduction in ASIC logic design: a methodology for clock tree management. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:4, pp:344-356 [Journal]
  132. Carlo Brandolese, Fabio Salice, William Fornaciari, Donatella Sciuto
    Static power modeling of 32-bit microprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:11, pp:1306-1316 [Journal]
  133. Roberto Cordone, Fabrizio Ferrandi, Donatella Sciuto, Roberto Wolfler Calvo
    An efficient heuristic approach to solve the unate covering problem. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:12, pp:1377-1388 [Journal]
  134. Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino, Donatella Sciuto
    Symbolic optimization of interacting controllers based onredundancy identification and removal. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:7, pp:760-772 [Journal]
  135. Fabrizio Lombardi, Donatella Sciuto, Renato Stefanelli
    An algorithm for functional reconfiguration of fixed-size arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:10, pp:1114-1118 [Journal]
  136. Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria
    An instruction-level energy model for embedded VLIW architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:9, pp:998-1010 [Journal]
  137. Luca Penzo, Donatella Sciuto, Cristina Silvano
    Construction techniques for systematic SEC-DED codes with single byte error detection and partial correction capability for computer memory systems. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Information Theory, 1995, v:41, n:2, pp:584-591 [Journal]
  138. Franco Fummi, U. Rovati, Donatella Sciuto
    Functional design for testability of control-dominated architectures. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1997, v:2, n:2, pp:98-122 [Journal]
  139. Giovanni Agosta, Francesco Bruschi, Gerardo Pelosi, Donatella Sciuto
    A Unified Approach to Canonical Form-based Boolean Matching. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:841-846 [Conf]
  140. Marco D. Santambrogio, Donatella Sciuto
    Partial Dynamic Reconfiguration: The Caronte Approach. A New Degree of Freedom in the HW/SW Codesign. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-2 [Conf]
  141. Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto, Boris Kettelhoit, Markus Köster, Mario Porrmann, Ulrich Rückert
    Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]
  142. Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto
    Dynamic Reconfigurability in Embedded System Design. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2734-2737 [Conf]
  143. Fabrizio Ferrandi, Pier Luca Lanzi, Gianluca Palermo, Christian Pilato, Donatella Sciuto, Antonino Tumeo
    An Evolutionary Approach to Area-Time Optimization of FPGA designs. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:145-152 [Conf]
  144. Simone Borgio, Davide Bosisio, Fabrizio Ferrandi, Matteo Monchiero, Marco D. Santambrogio, Donatella Sciuto, Antonino Tumeo
    Hardware DWT accelerator for MultiProcessor System-on-Chip on FPGA. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:107-114 [Conf]
  145. Antonino Tumeo, Marco Branca, Lorenzo Camerini, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
    An Interrupt Controller for FPGA-based Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:82-87 [Conf]
  146. Matteo Murgida, Alessandro Panella, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto
    Fast IP-Core Generation in a Partial Dynamic Reconfiguration Workflow. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:74-79 [Conf]
  147. Marco Giorgetta, Marco D. Santambrogio, Donatella Sciuto, Paola Spoletini
    A graph-coloring approach to the allocation and tasks scheduling for reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:24-29 [Conf]
  148. Giovanni Beltrame, Donatella Sciuto, Cristina Silvano, Pierre G. Paulin, Essaid Bensoudane
    An Application Mapping Methodology and Case Study for Multi-Processor On-Chip Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:146-151 [Conf]
  149. Alberto Donato, Fabrizio Ferrandi, Massimo Redaelli, Marco D. Santambrogio, Donatella Sciuto
    Caronte: A methodology for the Implementation of Partially dynamically Self-Reconfiguring Systems on FPGA Platforms. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:87-109 [Conf]
  150. Fabrizio Ferrandi, Luca Fossati, Marco Lattuada, Gianluca Palermo, Donatella Sciuto, Antonino Tumeo
    Automatic Parallelization of Sequential Specifications for Symmetric MPSoCs. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:179-192 [Conf]
  151. Cristiana Bolchini, Fabio Salice, Donatella Sciuto, Luigi Pomante
    Reliable System Specification for Self-Checking Data-Paths [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  152. Fabrizio Ferrandi, Franco Fummi, Graziano Pravadelli, Donatella Sciuto
    Identification of design errors through functional testing. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Reliability, 2003, v:52, n:4, pp:400-412 [Journal]
  153. Massimo Bombana, Giacomo Buonanno, Patrizia Cavalloro, Fabrizio Ferrandi, Donatella Sciuto, Giuseppe Zaza
    ALADIN: a multilevel testability analyzer for VLSI system design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:2, pp:157-171 [Journal]
  154. Cesare Alippi, Franco Fummi, Vincenzo Piuri, Mariagiovanna Sami, Donatella Sciuto
    Testability analysis and behavioral testing of the Hopfield neural paradigm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:3, pp:507-511 [Journal]
  155. William Fornaciari, P. Gubian, Donatella Sciuto, Cristina Silvano
    Power estimation of embedded systems: a hardware/software codesign approach. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:2, pp:266-275 [Journal]
  156. Franco Fummi, Donatella Sciuto, Cristina Silvano
    Automatic generation of error control codes for computer applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:3, pp:502-506 [Journal]
  157. Cristiana Bolchini, R. Montandon, Fabio Salice, Donatella Sciuto
    Design of VHDL-based totally self-checking finite-state machine and data-path descriptions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:1, pp:98-103 [Journal]
  158. Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon
    Low-power data forwarding for VLIW embedded architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:5, pp:614-622 [Journal]

  159. A Self-Reconfigurable Implementation of the JPEG Encoder. [Citation Graph (, )][DBLP]


  160. Lightweight DMA management mechanisms for multiprocessors on FPGA. [Citation Graph (, )][DBLP]


  161. Prototyping pipelined applications on a heterogeneous FPGA multiprocessor virtual platform. [Citation Graph (, )][DBLP]


  162. An application-centered design flow for self reconfigurable systems implementation. [Citation Graph (, )][DBLP]


  163. ReSP: A non-intrusive Transaction-Level Reflective MPSoC Simulation Platform for design space exploration. [Citation Graph (, )][DBLP]


  164. The Shining embedded system design methodology based on self dynamic reconfigurable architectures. [Citation Graph (, )][DBLP]


  165. Efficient pattern matching on GPUs for intrusion detection systems. [Citation Graph (, )][DBLP]


  166. Concurrency emulation and analysis of parallel applications for multi-processor system-on-chip co-design. [Citation Graph (, )][DBLP]


  167. Mapping pipelined applications onto heterogeneous embedded systems: a bayesian optimization algorithm based approach. [Citation Graph (, )][DBLP]


  168. Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems. [Citation Graph (, )][DBLP]


  169. Task Scheduling with Configuration Prefetching and Anti-Fragmentation techniques on Dynamically Reconfigurable Systems. [Citation Graph (, )][DBLP]


  170. A Dual-Priority Real-Time Multiprocessor System on FPGA for Automotive Applications. [Citation Graph (, )][DBLP]


  171. A novel methodology for designing TSC networks based on the parity bit code. [Citation Graph (, )][DBLP]


  172. A real-time application design methodology for MPSoCs. [Citation Graph (, )][DBLP]


  173. A reconfigurable multiprocessor architecture for a reliable face recognition implementation. [Citation Graph (, )][DBLP]


  174. A Requirements-Driven Reconfigurable SoC Communication Infrastructure Design Flow. [Citation Graph (, )][DBLP]


  175. A Design Workflow for the Identification of Area Constraints in Dynamic Reconfigurable Systems. [Citation Graph (, )][DBLP]


  176. A Generation Flow for Self-Reconfiguration Controllers Customization. [Citation Graph (, )][DBLP]


  177. A Framework for Reliability Assessment and Enhancement in Multi-Processor Systems-On-Chip. [Citation Graph (, )][DBLP]


  178. Fault Models and Injection Strategies in SystemC Specifications. [Citation Graph (, )][DBLP]


  179. Task Partitioning for the Scheduling on Reconfigurable Systems driven by Specification Self-Similarity. [Citation Graph (, )][DBLP]


  180. An architecture for dynamically reconfigurable real time audio processing systems. [Citation Graph (, )][DBLP]


  181. Testable synthesis of high complex control devices. [Citation Graph (, )][DBLP]


  182. The role of VHDL within the TOSCA hardware/software codesign framework. [Citation Graph (, )][DBLP]


  183. HW/SW methodologies for synchronization in FPGA multiprocessors. [Citation Graph (, )][DBLP]


  184. Operating system support for online partial dynamic reconfiguration management. [Citation Graph (, )][DBLP]


  185. A runtime relocation based workflow for self dynamic reconfigurable systems design. [Citation Graph (, )][DBLP]


  186. Evolutionary algorithms for the mapping of pipelined applications onto heterogeneous embedded systems. [Citation Graph (, )][DBLP]


  187. Multiprocessor systems-on-chip synthesis using multi-objective evolutionary computation. [Citation Graph (, )][DBLP]


  188. Reconfigurable NoC design flow for multiple applications run-time mapping on FPGA devices. [Citation Graph (, )][DBLP]


  189. A novel design framework for the design of reconfigurable systems based on NoCs. [Citation Graph (, )][DBLP]


  190. A novel SoC design methodology combining adaptive software and reconfigurable hardware. [Citation Graph (, )][DBLP]


  191. A design flow tailored for self dynamic reconfigurable architecture. [Citation Graph (, )][DBLP]


  192. Design methodology for partial dynamic reconfiguration: a new degree of freedom in the HW/SW codesign. [Citation Graph (, )][DBLP]


  193. HARPE: A Harvard-based processing element tailored for partial dynamic reconfigurable architectures. [Citation Graph (, )][DBLP]


  194. On-line task management for a reconfigurable cryptographic architecture. [Citation Graph (, )][DBLP]


  195. A multiprocessor self-reconfigurable JPEG2000 encoder. [Citation Graph (, )][DBLP]


  196. Core Allocation and Relocation Management for a Self Dynamically Reconfigurable Architecture. [Citation Graph (, )][DBLP]


  197. A Multi-objective Genetic Algorithm for Design Space Exploration in High-Level Synthesis. [Citation Graph (, )][DBLP]


  198. A light-weight Network-on-Chip architecture for dynamically reconfigurable systems. [Citation Graph (, )][DBLP]


  199. Ant colony optimization for mapping and scheduling in heterogeneous multiprocessor systems. [Citation Graph (, )][DBLP]


  200. An adaptive genetic algorithm for dynamically reconfigurable modules allocation. [Citation Graph (, )][DBLP]


  201. Fitness inheritance in evolutionary and multi-objective high-level synthesis. [Citation Graph (, )][DBLP]


  202. High-level synthesis with multi-objective genetic algorithm: A comparative encoding analysis. [Citation Graph (, )][DBLP]


  203. Aspect Orientation in System Level Design. [Citation Graph (, )][DBLP]


  204. Mapping Interface Method Calls over OCP Buses. [Citation Graph (, )][DBLP]


  205. An Internal Representation Model for System-Level Co-Design of Heterogeneous Multiprocessor Embedded System. [Citation Graph (, )][DBLP]


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