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Eugenio Villar: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Adrian López, Maite Veiga, Eugenio Villar
    Hardware/Software Embedded System Specifiaction and Design Using Ada and VHDL. [Citation Graph (0, 0)][DBLP]
    Ada-Europe, 1999, pp:356-370 [Conf]
  2. Masaharu Imai, Eugenio Villar
    Future direction of synthesizability and interoperability of HDL's: part 1. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  3. Hector Posadas, Jesús Ádamez, Pablo Sánchez, Eugenio Villar, Francisco Blasco
    POSIX modeling in SystemC. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:485-490 [Conf]
  4. Eugenio Villar, Masaharu Imai
    Future direction of synthesizabilty and interoperability of HDL's: part 2. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  5. F. Herrera, Eugenio Villar
    A framework for embedded system specification under different models of computation in SystemC. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:911-914 [Conf]
  6. Daniel Gajski, Eugenio Villar, Wolfgang Rosenstiel, Vassilios Gerousis, D. Barton, J. Plantin, S. E. Ericsson, Patrizia Cavalloro, Gjalt G. de Jong
    C/C++: progress or deadlock in system-level specification. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:136-137 [Conf]
  7. F. Herrera, Hector Posadas, Pablo Sánchez, Eugenio Villar
    Systemic Embedded Software Generation from SystemC. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10142-10149 [Conf]
  8. Hector Posadas, F. Herrera, Pablo Sánchez, Eugenio Villar, Francisco Blasco
    System-Level Performance Analysis in SystemC. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:378-383 [Conf]
  9. Masaharu Imai, Eugenio Villar
    ASPDAC 1995: HDL synthesizability and interoperability. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:1, pp:3-4 [Journal]
  10. Giulio Gorla, Eduard Moser, Wolfgang Nebel, Eugenio Villar
    System Specification Experiments on a Common Benchmark. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:3, pp:22-32 [Journal]
  11. Fernando Herrera, Eugenio Villar
    A framework for heterogeneous specification and design of electronic embedded systems in SystemC. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:3, pp:- [Journal]

  12. Heterogeneous System-level Specification Using SystemC. [Citation Graph (, )][DBLP]

  13. The ANDRES Project: Analysis and Design of Run-Time Reconfigurable, Heterogeneous Systems. [Citation Graph (, )][DBLP]

  14. Fast instruction cache modeling for approximate timed HW/SW co-simulation. [Citation Graph (, )][DBLP]

  15. AADL Simulation and Performance Analysis in SystemC. [Citation Graph (, )][DBLP]

  16. Automatic HW/SW Interface Modeling for Scratch-Pad and Memory Mapped HW Components in Native Source-Code Co-simulation. [Citation Graph (, )][DBLP]

  17. Specification of Adaptive HW/SW Systems in SystemC. [Citation Graph (, )][DBLP]

  18. A general approach to the interoperability of HetSC and SystemC-AMS. [Citation Graph (, )][DBLP]

  19. Protocol Bus Modeling using inheritance with TLM2.0. [Citation Graph (, )][DBLP]

  20. Extension of the SystemC Kernel for Simulation Coverage. [Citation Graph (, )][DBLP]

  21. Mixing Synchronous Reactive and Untimed Models of Computation. [Citation Graph (, )][DBLP]

  22. Heterogeneous System-Level Specification in SystemC. [Citation Graph (, )][DBLP]

  23. Modeling of CSP, KPN and SR Systems with SystemC. [Citation Graph (, )][DBLP]

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