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Sri Hari Krishna Narayanan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sri Hari Krishna Narayanan, Mahmut T. Kandemir, R. R. Brooks, Ibrahim Kolcu
    Secure Execution of Computations in Untrusted Hosts. [Citation Graph (0, 0)][DBLP]
    Ada-Europe, 2006, pp:106-118 [Conf]
  2. Sri Hari Krishna Narayanan, Seung Woo Son, Mahmut T. Kandemir, Feihui Li
    Using loop invariants to fight soft errors in data caches. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1317-1320 [Conf]
  3. Sri Hari Krishna Narayanan, Guilin Chen, Mahmut T. Kandemir, Yuan Xie
    Temperature-Sensitive Loop Parallelization for Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:677-682 [Conf]
  4. Hakduran Koc, Ozcan Ozturk, Mahmut T. Kandemir, Sri Hari Krishna Narayanan, Ehat Ercanli
    Minimizing energy consumption of banked memories using data recomputation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:358-362 [Conf]
  5. Sri Hari Krishna Narayanan, Mahmut T. Kandemir, Ozcan Ozturk
    Compiler-Directed Power Density Reduction in NoC-Based Multi-Core Designs. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:570-575 [Conf]
  6. S. H. K. Narayanan, Mahmut T. Kandemir, R. Brooks
    Performance aware secure code partitioning. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1122-1127 [Conf]

  7. A Systematic Approach to Automatically Generate Multiple Semantically Equivalent Program Versions. [Citation Graph (, )][DBLP]


  8. Slicing based code parallelization for minimizing inter-processor communication. [Citation Graph (, )][DBLP]


  9. Process variation aware thread mapping for Chip Multiprocessors. [Citation Graph (, )][DBLP]


  10. In-Network Caching for Chip Multiprocessors. [Citation Graph (, )][DBLP]


  11. A Scratch-Pad Memory Aware Dynamic Loop Scheduling Algorithm. [Citation Graph (, )][DBLP]


  12. Compiler directed network-on-chip reliability enhancement for chip multiprocessors. [Citation Graph (, )][DBLP]


  13. Optimizing shared cache behavior of chip multiprocessors. [Citation Graph (, )][DBLP]


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