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Renato Fernandes Hentschke: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Júlio C. B. de Mattos, Lisane B. de Brisolara, Renato Fernandes Hentschke, Luigi Carro, Flávio Rech Wagner
    Design Space Exploration with Automatic Generation of IP-Based Embedded Software. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:237-246 [Conf]
  2. Renato Fernandes Hentschke, Ricardo Reis
    Plic-Plac: a novel constructive algorithm for placement. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:461-464 [Conf]
  3. Renato Fernandes Hentschke, Guilherme Flach, Felipe Pinto, Ricardo Reis
    3D-Vias Aware Quadratic Placement for 3D VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:67-72 [Conf]
  4. Renato Fernandes Hentschke, Guilherme Flach, Felipe Pinto, Ricardo Reis
    Quadratic placement for 3d circuits using z-cell shifting, 3d iterative refinement and simulated annealing. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:220-225 [Conf]
  5. Renato Fernandes Hentschke, Jagannathan Narasimhan, David Kung
    Improving run times by pruned application of synthesis transforms. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2005, pp:38-43 [Conf]
  6. Renato Fernandes Hentschke, Ricardo Augusto da Luz Reis
    Improving Simulated Annealing Placement by Applying Random and Greedy Mixed Perturbations. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:267-0 [Conf]
  7. Renato Fernandes Hentschke, Marcelo de Oliveira Johann, Ricardo Augusto da Luz Reis
    A study on the performance of fast initial placement algorithms. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:204-0 [Conf]
  8. Fernanda Lima Kastensmidt, Gustavo Neuberger, Renato Fernandes Hentschke, Luigi Carro, Ricardo Reis
    Designing Fault-Tolerant Techniques for SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:6, pp:552-562 [Journal]
  9. Renato Fernandes Hentschke, Ricardo Reis
    A 3D-Via Legalization Algorithm for 3D VLSI Circuits and its Impact on Wire Length. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2036-2039 [Conf]
  10. Renato Fernandes Hentschke, Jaganathan Narasimham, Marcelo O. Johann, Ricardo Augusto da Luz Reis
    Maze routing steiner trees with effective critical sink optimization. [Citation Graph (0, 0)][DBLP]
    ISPD, 2007, pp:135-142 [Conf]
  11. Renato Fernandes Hentschke, Sandro Sawicki, Marcelo de Oliveira Johann, Ricardo Augusto da Luz Reis
    An Algorithm for I/O Partitioning Targeting 3D Circuits and Its Impact on 3D-Vias. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:128-133 [Conf]

  12. Exact route matching algorithms for analog and mixed signal integrated circuits. [Citation Graph (, )][DBLP]


  13. Cell placement on graphics processing units. [Citation Graph (, )][DBLP]


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