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Denis Flandre: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Amaury Nève, Denis Flandre
    Design of a Branch-Based Carry-Select Adder IP Portable in 0.25 µm Bulk and Silicon-On-Insulator CMOS Technologies. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:169-180 [Conf]
  2. David Levacq, Vincent Dessard, Denis Flandre
    Ultra-low power flip-flops for MTCMOS circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4681-4684 [Conf]
  3. Amaury Nève, Denis Flandre, Helmut Schettler, Thomas Ludwig 0004, Gerhard Hellner
    Design of a branch-based 64-bit carry-select adder in 0.18 µm partially depleted SOI CMOS. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:108-111 [Conf]
  4. Ilham Hassoune, Amaury Nève, Jean-Didier Legat, Denis Flandre
    Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:189-197 [Conf]
  5. Salvador Pinillos Gimenez, Marcelo Antonio Pavanello, J. A. Martino, S. Adriaensen, Denis Flandre
    Design of Operational Transconductance Amplifiers with Improved Gain by Using Graded-Channel SOI nMOSFETs. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:26-0 [Conf]
  6. Amaury Nève, Denis Flandre, Jean-Jacques Quisquater
    SOI Technology for Future High-Performance Smart Cards. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:3, pp:58-67 [Journal]
  7. Amaury Nève, Helmut Schettler, Thomas Ludwig 0004, Denis Flandre
    Power-delay product minimization in high-performance 64-bit carry-select adders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:3, pp:235-244 [Journal]
  8. Marcelo Antonio Pavanello, Paula Ghedini Der Agopian, João Antonio Martino, Denis Flandre
    Cryogenic operation of graded-channel silicon-on-insulator nMOSFETs for high performance analog applications. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2006, v:37, n:2, pp:137-144 [Journal]
  9. Ilham Hassoune, François Macé, Denis Flandre, Jean-Didier Legat
    Low-swing current mode logic (LSCML): A new logic style for secure and robust smart cards against power analysis attacks. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2006, v:37, n:9, pp:997-1006 [Journal]
  10. Salvador Pinillos Gimenez, Marcelo Antonio Pavanello, João Antonio Martino, Denis Flandre
    Gain improvement in operational transconductance amplifiers using Graded-Channel SOI nMOSFETS. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2006, v:37, n:1, pp:31-37 [Journal]
  11. Ilham Hassoune, François Macé, Denis Flandre, Jean-Didier Legat
    Dynamic differential self-timed logic families for robust and low-power security ICs. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:3, pp:355-364 [Journal]

  12. Analysis and minimization of practical energy in 45nm subthreshold logic circuits. [Citation Graph (, )][DBLP]


  13. Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic. [Citation Graph (, )][DBLP]


  14. Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits. [Citation Graph (, )][DBLP]


  15. Systematic HDL Design of a Delta-Sigma Fractional-N Phase-Locked Loop for Wireless Applications. [Citation Graph (, )][DBLP]


  16. Impact of Technology Scaling on Digital Subthreshold Circuits. [Citation Graph (, )][DBLP]


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