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Bernabé Linares-Barranco: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Teresa Serrano-Gotarredona, Bernabé Linares-Barranco, Andreas G. Andreou
    Programmable Kernel Analog VLSI Convolution Chip for Real Time Vision Processing. [Citation Graph (0, 0)][DBLP]
    IJCNN (4), 2000, pp:62-65 [Conf]
  2. Servando Espejo-Meana, Ángel Rodríguez-Vázquez, Rafael Domínguez-Castro, Bernabé Linares-Barranco, José Luis Huertas
    A Model for VLSI Implementation of CNN Image Processing Chips Using Current-mode Techniques. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:970-973 [Conf]
  3. Bernabé Linares-Barranco, Teresa Serrano-Gotarredona, Rafael Serrano-Gotarredona, Jesús Costas-Santos
    A new charge-packet driven mismatch-calibrated integrate-and-fire neuron for processing positive and negative signals in AER based systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:744-747 [Conf]
  4. Alejandro Linares-Barranco, Gabriel Jiménez-Moreno, Antón Civit-Balcells, Bernabé Linares-Barranco
    On synthetic AER generation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:784-787 [Conf]
  5. Bernabé Linares-Barranco, Teresa Serrano-Gotarredona, Rafael Serrano-Gotarredona, Gustavo Vicente-Sánchez
    On mismatch properties of MOS and resistors calibrated ladder structures. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:377-380 [Conf]
  6. Bernabé Linares-Barranco, Teresa Serrano-Gotarredona, J. Ramos-Martos, J. Ceballos-Cáaceres, J. M. Mora, Alejandro Linares-Barranco
    A precise 90/spl deg/ quadrature OTA-C VCO between 50-130 MHz. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:541-544 [Conf]
  7. Bernabé Linares-Barranco, Teresa Serrano-Gotarredona, Rafael Serrano-Gotarredona, Luis A. Camuñas
    On leakage current temperature characterization using sub-pico-ampere circuit techniques. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:361-364 [Conf]
  8. Teresa Serrano-Gotarredona, Bernabé Linares-Barranco
    Experimental Results of an Analog Current-Mode ART1 Chip. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1672-1675 [Conf]
  9. Teresa Serrano-Gotarredona, Bernabé Linares-Barranco, Jesús Velarde-Ramírez
    A precise CMOS mismatch model for analog design from weak to strong inversion. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:753-756 [Conf]
  10. Teresa Serrano-Gotarredona, Rafael Serrano-Gotarredona, Bernabé Linares-Barranco
    Hardware implementation of complex reaction-diffusion neural networks using log-domain techniques. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:301-304 [Conf]
  11. Teresa Serrano-Gotarredona, Bernabé Linares-Barranco
    A Modular Current-Mode High-Precision Winner-Take-All Circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:557-560 [Conf]
  12. Teresa Serrano-Gotarredona, Bernabé Linares-Barranco, Andreas G. Andreou
    A general subthreshold MOS translinear theorem. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 1999, pp:302-305 [Conf]
  13. Teresa Serrano-Gotarredona, Andreas G. Andreou, Bernabé Linares-Barranco
    Programmable 2D image filter for AER vision processing. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 1999, pp:159-162 [Conf]
  14. Alejandro Linares-Barranco, Matthias Oster, D. Cascado, Gabriel Jiménez, Antón Civit, Bernabé Linares-Barranco
    Inter-spike-intervals Analysis of Poisson Like Hardware Synthetic AER Generation. [Citation Graph (0, 0)][DBLP]
    IWANN, 2005, pp:479-485 [Conf]
  15. Bernabé Linares-Barranco, S. Sánchez-Sinencio, Ángel Rodríguez-Vázquez, José Luis Huertas
    CMOS Continuous BAM With On Chip Learning. [Citation Graph (0, 0)][DBLP]
    IWANN, 1991, pp:322-327 [Conf]
  16. Teresa Serrano-Gotarredona, Bernabé Linares-Barranco
    Adaptive Resonance Theory Microchips. [Citation Graph (0, 0)][DBLP]
    IWANN (1), 1999, pp:737-746 [Conf]
  17. Teresa Serrano-Gotarredona, Bernabé Linares-Barranco, José Luis Huertas
    A Real Time Clustering CMOS Neural Engine. [Citation Graph (0, 0)][DBLP]
    NIPS, 1994, pp:755-762 [Conf]
  18. Rafael Serrano-Gotarredona, Matthias Oster, Patrick Lichtsteiner, Alejandro Linares-Barranco, R. Paz-Vicente, F. Gomez-Rodriguez, Håvard Kolle Riis, Tobi Delbrück, Shih-Chii Liu, S. Zahnd, Adrian M. Whatley, Rodney J. Douglas, Philipp Häfliger, Gabriel Jiménez-Moreno, Antón Civit, Teresa Serrano-Gotarredona, A. Acosta-Jimenez, Bernabé Linares-Barranco
    AER Building Blocks for Multi-Layer Multi-Chip Neuromorphic Vision Systems. [Citation Graph (0, 0)][DBLP]
    NIPS, 2005, pp:- [Conf]
  19. Alejandro Linares-Barranco, Gabriel Jiménez, Antón Civit, Bernabé Linares-Barranco
    Synthetic Generation of Events for Address-Event-Representation Communications. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:371-379 [Conf]
  20. Teresa Serrano-Gotarredona, Andreas G. Andreou, Bernabé Linares-Barranco
    A Programmable VLSI Filter Architecture for Application in Real-Time Vision Processing Systems. [Citation Graph (0, 0)][DBLP]
    Int. J. Neural Syst., 2000, v:10, n:3, pp:179-190 [Journal]
  21. Teresa Serrano-Gotarredona, Bernabé Linares-Barranco
    A Modified ART 1 Algorithm more Suitable for VLSI Implementations. [Citation Graph (0, 0)][DBLP]
    Neural Networks, 1996, v:9, n:6, pp:1025-1043 [Journal]
  22. Jesús Costas-Santos, Teresa Serrano-Gotarredona, Rafael Serrano-Gotarredona, Bernabé Linares-Barranco
    An AER Contrast Retina with On-Chip Calibration. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3075-3078 [Conf]
  23. Rafael Serrano-Gotarredona, Teresa Serrano-Gotarredona, A. Acosta-Jimenez, Alejandro Linares-Barranco, Gabriel Jiménez-Moreno, Antón Civit-Balcells, Bernabé Linares-Barranco
    Spike Events Processing for Vision Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:841-844 [Conf]
  24. Bernabé Linares-Barranco, Teresa Serrano-Gotarredona
    A Physical Interpretation of the Distance Term in Pelgrom's Mismatch Model results in very Efficient CAD. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1561-1564 [Conf]
  25. Rafael Serrano-Gotarredona, Bernabé Linares-Barranco, Teresa Serrano-Gotarredona, A. Acosta-Jimenez, Alejandro Linares-Barranco, R. Paz-Vicente, F. Gomez-Rodriguez
    High-speed image processing with AER-based components. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  26. Alejandro Linares-Barranco, D. Cascado, Gabriel Jiménez, Antón Civit, Matthias Oster, Bernabé Linares-Barranco
    Poisson AER generator: inter-spike-intervals analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  27. Rafael Serrano-Gotarredona, Teresa Serrano-Gotarredona, A. Acosta-Jimenez, Bernabé Linares-Barranco
    An arbitrary kernel convolution AER-transceiver chip for real-time image filtering. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  28. Alejandro Linares-Barranco, Matthias Oster, D. Cascado, Gabriel Jiménez, Antón Civit, Bernabé Linares-Barranco
    Inter-spike-intervals analysis of AER Poisson-like generator hardware. [Citation Graph (0, 0)][DBLP]
    Neurocomputing, 2007, v:70, n:16-18, pp:2692-2700 [Journal]
  29. Teresa Serrano-Gotarredona, Bernabé Linares-Barranco
    A real-time clustering microchip neural engine. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:2, pp:195-209 [Journal]

  30. Advanced Vision Processing Systems: Spike-Based Simulation and Processing. [Citation Graph (, )][DBLP]


  31. Event based vision sensing and processing. [Citation Graph (, )][DBLP]


  32. LVDS interface for AER links with burst mode operation capability. [Citation Graph (, )][DBLP]


  33. Compact calibration circuit for large neuromorphic arrays. [Citation Graph (, )][DBLP]


  34. High-speed character recognition system based on a complex hierarchical AER architecture. [Citation Graph (, )][DBLP]


  35. Fully digital AER convolution chip for vision processing. [Citation Graph (, )][DBLP]


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