Kentaroh Katoh, Hideo Ito Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices. [Citation Graph (0, 0)][DBLP] European Test Symposium, 2006, pp:69-74 [Conf]
A Delay Measurement Technique Using Signature Registers. [Citation Graph (, )][DBLP]
Fault Tolerant SoC Architecture Design for JPEG2000 Using Partial Reconfigurability. [Citation Graph (, )][DBLP]
Search in 0.001secs, Finished in 0.001secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP