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Ulrich Rückert: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Matthias Grünewald, Feng Xu, Ulrich Rückert
    Increasing the Resource-Efficiency of the CSMA/CA Protocol in Directional Ad Hoc Networks. [Citation Graph (0, 0)][DBLP]
    ADHOC-NOW, 2005, pp:71-84 [Conf]
  2. Axel Löffler, Jürgen Klahold, Ulrich Rückert
    The Dynamical Nightwatch's Problem Solved by the Autonomous Micro-Robot Khepera. [Citation Graph (0, 0)][DBLP]
    Artificial Evolution, 1997, pp:303-314 [Conf]
  3. Teerapat Chinapirom, Ulf Witkowski, Ulrich Rückert
    Universal FPGA-Microcontroller Module for Autonomous Minirobots. [Citation Graph (0, 0)][DBLP]
    AMiRE, 2005, pp:21-26 [Conf]
  4. Jia Lei Du, Ulf Witkowski, Ulrich Rückert
    Teleoperation of a Mobile Autonomous Robot using Web Services. [Citation Graph (0, 0)][DBLP]
    AMiRE, 2005, pp:55-60 [Conf]
  5. Andry Tanoto, Ulf Witkowski, Ulrich Rückert
    Teleworkbench: A Teleoperated Platform for Multi-Robot Experiments. [Citation Graph (0, 0)][DBLP]
    AMiRE, 2005, pp:49-54 [Conf]
  6. Heiko Kalte, Mario Porrmann, Ulrich Rückert
    Leistungsbewertung unterschiedlicher Einbettungsvariaten dynamisch rekonfigurierbarer Hardware. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2004, pp:235-244 [Conf]
  7. Jörg-Christian Niemann, Christoph Puttmann, Mario Porrmann, Ulrich Rückert
    GigaNetIC - A Scalable Embedded On-Chip Multiprocessor Architecture for Network Applications. [Citation Graph (0, 0)][DBLP]
    ARCS, 2006, pp:268-282 [Conf]
  8. Jörg-Christian Niemann, Christian Liß, Mario Porrmann, Ulrich Rückert
    A Multiprocessor Cache for Massively Parallel SoC Architectures. [Citation Graph (0, 0)][DBLP]
    ARCS, 2007, pp:83-97 [Conf]
  9. Bjørn Jager, Jörg-Christian Niemann, Ulrich Rückert
    Analytical approach to massively parallel architectures for nanotechnologies. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:268-275 [Conf]
  10. Matthias Grünewald, Jörg-Christian Niemann, Mario Porrmann, Ulrich Rückert
    A Mapping Strategy for Resource-Efficient Network Processing on Multiprocessor SoC. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:758-763 [Conf]
  11. Axel Löffler, Jürgen Klahold, Manfred Hußmann, Ulrich Rückert
    A Visualization Tool for the Mini-Robot Khepera: Behavior Analysis and Optimization. [Citation Graph (0, 0)][DBLP]
    ECAL, 1999, pp:329-333 [Conf]
  12. Elisabeth Georgii, Lothar Richter, Ulrich Rückert, Stefan Kramer
    Analyzing microarray data using quantitative association rules. [Citation Graph (0, 0)][DBLP]
    ECCB/JBI, 2005, pp:129- [Conf]
  13. Ulrich Rückert, Stefan Kramer, Luc De Raedt
    Phase Transitions and Stochastic Local Search in k-Term DNF Learning. [Citation Graph (0, 0)][DBLP]
    ECML, 2002, pp:405-417 [Conf]
  14. Heiko Kalte, Markus Koester, Boris Kettelhoit, Mario Porrmann, Ulrich Rückert
    A Comparative Study on System Approaches for Partially Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    ERSA, 2004, pp:70-76 [Conf]
  15. Ralf Eickhoff, Joaquin Sitte, Ulrich Rückert
    Robust Local Cluster Neural Networks. [Citation Graph (0, 0)][DBLP]
    ESANN, 2006, pp:119-124 [Conf]
  16. Mario Porrmann, Marc Franzmeier, Heiko Kalte, Ulf Witkowski, Ulrich Rückert
    A reconfigurable SOM hardware accelerator. [Citation Graph (0, 0)][DBLP]
    ESANN, 2002, pp:337-342 [Conf]
  17. Ulrich Rückert
    VLSI Implementation of an Associative Memory Based on Distributed Storage of Information. [Citation Graph (0, 0)][DBLP]
    EURASIP Workshop, 1990, pp:267-276 [Conf]
  18. Mario Porrmann, Ulrich Rückert, Karl Michael Marks, Jörg Landmann
    HiBRIC-MEM, a Memory Controller for PowerPC Based Systems. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1997, pp:653-657 [Conf]
  19. André Brinkmann, Dominik Langen, Ulrich Rückert
    A Rapid Prototyping Environment for Microprocessor Based System-on-Chips and Its Application to the Development of a Network Processor. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:838-841 [Conf]
  20. Björn Griese, Erik Vonnahme, Mario Porrmann, Ulrich Rückert
    Hardware Support for Dynamic Reconfiguration in Reconfigurable SoC Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:842-846 [Conf]
  21. Mario Porrmann, Ulf Witkowski, Heiko Kalte, Ulrich Rückert
    Dynamically Reconfigurable Hardware - A New Perspective for Neural Network Implementations. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1048-1057 [Conf]
  22. Chris Loeser, André Brinkmann, Ulrich Rückert
    Distributed Path Selection (DPS) A Traf.c Engineering Protocol for IP-Networks. [Citation Graph (0, 0)][DBLP]
    HICSS, 2004, pp:- [Conf]
  23. Ralf Eickhoff, Ulrich Rückert
    Tolerance of Radial Basis Functions Against Stuck-At-Faults. [Citation Graph (0, 0)][DBLP]
    ICANN (2), 2005, pp:1003-1008 [Conf]
  24. Ralf Eickhoff, Ulrich Rückert
    Pareto-optimal Noise and Approximation Properties of RBF Networks. [Citation Graph (0, 0)][DBLP]
    ICANN (1), 2006, pp:993-1002 [Conf]
  25. Burkhard Iske, Axel Löffler, Ulrich Rückert
    A Direction Sensitive Network Based on a Biophysical Neurone Model. [Citation Graph (0, 0)][DBLP]
    ICANN, 2002, pp:153-159 [Conf]
  26. Ulrich Rückert, Lothar Richter, Stefan Kramer
    Quantitative Association Rules Based on Half-Spaces: An Optimization Approach. [Citation Graph (0, 0)][DBLP]
    ICDM, 2004, pp:507-510 [Conf]
  27. Ulrich Rückert, Stefan Kramer
    Stochastic Local Search in k-Term DNF Learning. [Citation Graph (0, 0)][DBLP]
    ICML, 2003, pp:648-655 [Conf]
  28. Ulrich Rückert, Stefan Kramer
    Towards tight bounds for rule learning. [Citation Graph (0, 0)][DBLP]
    ICML, 2004, pp:- [Conf]
  29. Ulrich Rückert, Stefan Kramer
    A statistical approach to rule learning. [Citation Graph (0, 0)][DBLP]
    ICML, 2006, pp:785-792 [Conf]
  30. Burkhard Iske, Ulrich Rückert, Kurt Malmstrom, Joaquin Sitte
    A Bootstrapping Method for Autonomous and in Site Learning of Generic Navigation Behavior. [Citation Graph (0, 0)][DBLP]
    ICPR, 2000, pp:4656-4659 [Conf]
  31. Jürgen Klahold, Jens Rautenberg, Ulrich Rückert
    Continuous Sonar Sensing for Mobile Mini-Robots. [Citation Graph (0, 0)][DBLP]
    ICRA, 2002, pp:323-328 [Conf]
  32. Heiko Kalte, Gareth Lee, Mario Porrmann, Ulrich Rückert
    REPLICA: A Bitstream Manipulation Filter for Module Relocation in Partial Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  33. Heiko Kalte, Mario Porrmann, Ulrich Rückert
    System-on-Programmable-Chip Approach Enabling Online Fine-Grained 1D-Placement. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  34. Markus Koester, Mario Porrmann, Ulrich Rückert
    Placement-Oriented Modeling of Partially Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  35. Jörg-Christian Niemann, Mario Porrmann, Ulrich Rückert
    A Scalable Parallel SoC Architecture for Network Processors. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:311-313 [Conf]
  36. Ralf Eickhoff, Ulrich Rückert
    Robustness of Radial Basis Functions. [Citation Graph (0, 0)][DBLP]
    IWANN, 2005, pp:264-271 [Conf]
  37. Marc Franzmeier, Ulf Witkowski, Ulrich Rückert
    Explorative Data Analysis Based on Self-organizing Maps and Automatic Map Analysis. [Citation Graph (0, 0)][DBLP]
    IWANN, 2005, pp:725-733 [Conf]
  38. Karl Goser, U. Hilleringmann, Ulrich Rückert
    Application and Implementation of Neural Networks in Microelectronics. [Citation Graph (0, 0)][DBLP]
    IWANN, 1991, pp:243-259 [Conf]
  39. Tim Kaulmann, Markus Ferber, Ulf Witkowski, Ulrich Rückert
    Analog VLSI Implementation of Adaptive Synapses in Pulsed Neural Networks. [Citation Graph (0, 0)][DBLP]
    IWANN, 2005, pp:455-462 [Conf]
  40. Stefan Rüping, Mario Porrmann, Ulrich Rückert
    A High Performance SOFM Hardware-System. [Citation Graph (0, 0)][DBLP]
    IWANN, 1997, pp:772-781 [Conf]
  41. Stefan Rüping, Ulrich Rückert, Karl Goser
    Hardware Design for Self-Organizing Feature Maps with Binary Input Vectors. [Citation Graph (0, 0)][DBLP]
    IWANN, 1993, pp:488-493 [Conf]
  42. Matthias Grünewald, Jörg-Christian Niemann, Ulrich Rückert
    A performance evaluation method for optimizing embedded applications. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:10-15 [Conf]
  43. Ulrich Rückert, Stefan Kramer
    Generalized Version Space Trees. [Citation Graph (0, 0)][DBLP]
    KDID, 2003, pp:119-129 [Conf]
  44. Olaf Bonorden, Nikolaus Brüls, Uwe Kastens, Dinh Khoi Le, Friedhelm Meyer auf der Heide, Jörg-Christian Niemann, Mario Porrmann, Ulrich Rückert, Adrian Slowik, Michael Thies
    A holistic methodology for network processor design. [Citation Graph (0, 0)][DBLP]
    LCN, 2003, pp:583-0 [Conf]
  45. Marc Franzmeier, Christopher Pohl, Mario Porrmann, Ulrich Rückert
    Hardware Accelerated Data Analysis. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2004, pp:309-314 [Conf]
  46. Matthias Grünewald, Dinh Khoi Le, Uwe Kastens, Jörg-Christian Niemann, Mario Porrmann, Ulrich Rückert, Adrian Slowik, Michael Thies
    Network Application Driven Instruction Set Extensions for Embedded Processing Clusters. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2004, pp:209-214 [Conf]
  47. Erik Vonnahme, Björn Griese, Mario Porrmann, Ulrich Rückert
    Dynamic Reconfiguration of Real-Time Network Interfaces. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2004, pp:376-379 [Conf]
  48. Heiko Kalte, Dominik Langen, Erik Vonnahme, André Brinkmann, Ulrich Rückert
    Dynamically Reconfigurable System-on-Programmable-Chip. [Citation Graph (0, 0)][DBLP]
    PDP, 2002, pp:235-242 [Conf]
  49. Mario Porrmann, Ulf Witkowski, Heiko Kalte, Ulrich Rückert
    Implementation of Artificial Neural Networks on a Reconfigurable Hardware Accelerator. [Citation Graph (0, 0)][DBLP]
    PDP, 2002, pp:243-0 [Conf]
  50. Heiko Kalte, Mario Porrmann, Ulrich Rückert
    Using a Dynamically Reconfigurable System to Accelerate Octree Based 3D Graphics. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2000, pp:- [Conf]
  51. Lothar Richter, Ulrich Rückert, Stefan Kramer
    Learning a Predictive Model for Growth Inhibition from the NCI DTP Human Tumor Cell Line Screening Data: Does Gene Expression Make a Difference? [Citation Graph (0, 0)][DBLP]
    Pacific Symposium on Biocomputing, 2006, pp:596-607 [Conf]
  52. Ulrich Rückert, Stefan Kramer
    Frequent free tree discovery in graph data. [Citation Graph (0, 0)][DBLP]
    SAC, 2004, pp:564-570 [Conf]
  53. Karl Goser, Karl Michael Marks, Ulrich Rückert, V. Tryba
    Selbstorganisierende Parameterkarten zur Prozeßüberwachung und -voraussage. [Citation Graph (0, 0)][DBLP]
    Wissensbasierte Systeme, 1989, pp:227-237 [Conf]
  54. Günther Palm, Ulrich Rückert, Alfred Ultsch
    Wissensverarbeitung in neuronaler Architektur. [Citation Graph (0, 0)][DBLP]
    Wissensbasierte Systeme, 1991, pp:508-518 [Conf]
  55. Ulrich Rückert, Karl Goser
    Adaptive Associate Systems for VLSI. [Citation Graph (0, 0)][DBLP]
    WOPPLOT, 1986, pp:166-184 [Conf]
  56. Ulrich Rückert, Andreas Funke, Christof Pintaske
    Acceleratorboard for neural associative memories. [Citation Graph (0, 0)][DBLP]
    Neurocomputing, 1993, v:5, n:1, pp:39-49 [Journal]
  57. Stefan Rüping, Mario Porrmann, Ulrich Rückert
    SOM accelerator system. [Citation Graph (0, 0)][DBLP]
    Neurocomputing, 1998, v:21, n:1-3, pp:31-50 [Journal]
  58. Martin Schæfer, Tim Schönauer, Carsten Wolff, Georg Hartmann, Heinrich Klar, Ulrich Rückert
    Simulation of spiking neural networks -- architectures and implementations. [Citation Graph (0, 0)][DBLP]
    Neurocomputing, 2002, v:48, n:1-4, pp:647-679 [Journal]
  59. Joaquin Sitte, Tim Körner, Ulrich Rückert
    Local cluster neural net analog VLSI design. [Citation Graph (0, 0)][DBLP]
    Neurocomputing, 1998, v:19, n:1-3, pp:185-197 [Journal]
  60. Karl Goser, Carsten Foelster, Ulrich Rückert
    Intelligent memories in VLSI. [Citation Graph (0, 0)][DBLP]
    Inf. Sci., 1984, v:34, n:1, pp:61-82 [Journal]
  61. Ulrich Rückert
    ULSI Architectures for Artificial Neural Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2002, v:22, n:3, pp:10-19 [Journal]
  62. Ulrich Rückert, Stefan Kramer
    Optimizing Feature Sets for Structured Data. [Citation Graph (0, 0)][DBLP]
    ECML, 2007, pp:716-723 [Conf]
  63. Tim Kaulmann, Axel Löffler, Ulrich Rückert
    A Control Approach to a Biophysical Neuron Model. [Citation Graph (0, 0)][DBLP]
    ICANN (1), 2007, pp:529-538 [Conf]
  64. Ralf Eickhoff, Tim Kaulmann, Ulrich Rückert
    Impact of Shrinking Technologies on the Activation Function of Neurons. [Citation Graph (0, 0)][DBLP]
    ICANN (1), 2007, pp:501-510 [Conf]
  65. Michael Grosseschallau, Ulf Witkowski, Ulrich Rückert
    Low-cost Bluetooth Communication for the Autonomous Mobile Minirobot Khepera. [Citation Graph (0, 0)][DBLP]
    ICRA, 2005, pp:4194-4199 [Conf]
  66. Ulrich Rückert, Stefan Kramer
    Margin-Based First-Order Rule Learning. [Citation Graph (0, 0)][DBLP]
    ILP, 2006, pp:46-48 [Conf]
  67. Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto, Boris Kettelhoit, Markus Köster, Mario Porrmann, Ulrich Rückert
    Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]
  68. Bjørn Jager, Mario Porrmann, Ulrich Rückert
    Bio-inspired massively parallel architectures for nanotechnologies. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  69. Ralf Eickhoff, Tim Kaulmann, Ulrich Rückert
    Neural Inspired Architectures for Nanoelectronics. [Citation Graph (0, 0)][DBLP]
    IWANN, 2007, pp:414-421 [Conf]
  70. Tim Kaulmann, Sven Lütkemeier, Ulrich Rückert
    IAF Neuron Implementation for Mixed-Signal PCNN Hardware. [Citation Graph (0, 0)][DBLP]
    IWANN, 2007, pp:447-454 [Conf]
  71. Markus Koester, Heiko Kalte, Mario Porrmann, Ulrich Rückert
    Defragmentation Algorithms for Partially Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:41-53 [Conf]
  72. Ralf Eickhoff, Ulrich Rückert
    Robustness of radial basis functions. [Citation Graph (0, 0)][DBLP]
    Neurocomputing, 2007, v:70, n:16-18, pp:2758-2767 [Journal]
  73. Jörg-Christian Niemann, Christoph Puttmann, Mario Porrmann, Ulrich Rückert
    Resource efficiency of the GigaNetIC chip multiprocessor architecture. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:5-6, pp:285-299 [Journal]

  74. GigaNoC - A Hierarchical Network-on-Chip for Scalable Chip-Multiprocessors. [Citation Graph (, )][DBLP]

  75. Using Run-time Reconfiguration for Energy Savings in Parallel Data Processing. [Citation Graph (, )][DBLP]

  76. Controlling complexity of RBF networks by similarity. [Citation Graph (, )][DBLP]

  77. A Digital Framework for Pulse Coded Neural Network Hardware with Bit-Serial Operation. [Citation Graph (, )][DBLP]

  78. Modified Local Navigation Strategy for Unknown Environment Exploration. [Citation Graph (, )][DBLP]

  79. Robot Localization based on Visual Landmarks. [Citation Graph (, )][DBLP]

  80. Enhancing Fault Tolerance of Radial Basis Functions. [Citation Graph (, )][DBLP]

  81. SIRENS: A Simple Reconfigurable Neural Hardware Structure for artificial neural network implementations. [Citation Graph (, )][DBLP]

  82. V: Drive - Costs and Benefits of an Out-of-Band Storage Virtualization System. [Citation Graph (, )][DBLP]

  83. ULSI Architectures for Artificial Neural Networks. [Citation Graph (, )][DBLP]

  84. Content-Based Information Retrieval Using an Embedded Neural Associative Memory. [Citation Graph (, )][DBLP]

  85. Kernel-Based Inductive Transfer. [Citation Graph (, )][DBLP]

  86. Capacity Control for Partially Ordered Feature Sets. [Citation Graph (, )][DBLP]

  87. Fast, Effective Molecular Feature Mining by Local Optimization. [Citation Graph (, )][DBLP]

  88. A Unifying View of Multiple Kernel Learning. [Citation Graph (, )][DBLP]

  89. Adaptive Concept Drift Detection. [Citation Graph (, )][DBLP]

  90. A Synchronization Method for Register Traces of Pipelined Processors. [Citation Graph (, )][DBLP]

  91. Teleworkbench: An Analysis Tool for Multi-Robotic Experiments. [Citation Graph (, )][DBLP]

  92. An automated platform for minirobots experiments. [Citation Graph (, )][DBLP]

  93. Vision Module for Mini-robots Providing Optical Flow Processing for Obstacle Avoidance. [Citation Graph (, )][DBLP]

  94. Topology Control in Large-Scale High Dynamic Mobile Ad-Hoc Networks. [Citation Graph (, )][DBLP]

  95. Ad-Hoc Communication and Localization System for Mobile Robots. [Citation Graph (, )][DBLP]

  96. Design Space Exploration for Memory Subsystems of VLIW Architectures. [Citation Graph (, )][DBLP]

  97. UMAC - A Universal MAC architecture for heterogeneous home networks. [Citation Graph (, )][DBLP]

  98. An experimental evaluation of simplicity in rule learning. [Citation Graph (, )][DBLP]

  99. A Unifying View of Multiple Kernel Learning [Citation Graph (, )][DBLP]

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