The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Ingrid Verbauwhede: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. David Hwang, Bo-Cheng Lai, Ingrid Verbauwhede
    Energy-Memory-Security Tradeoffs in Distributed Sensor Networks. [Citation Graph (0, 0)][DBLP]
    ADHOC-NOW, 2004, pp:70-81 [Conf]
  2. Herwin Chan, Miguel Griot, Andres I. Vila Casado, Richard D. Wesel, Ingrid Verbauwhede
    High Speed Channel Coding Architectures for the Uncoordinated OR Channel. [Citation Graph (0, 0)][DBLP]
    ASAP, 2006, pp:265-268 [Conf]
  3. Lejla Batina, Nele Mentens, Bart Preneel, Ingrid Verbauwhede
    Side-channel aware design: Algorithms and Architectures for Elliptic Curve Cryptography over GF(2n). [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:350-355 [Conf]
  4. Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, Ingrid Verbauwhede
    Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip. [Citation Graph (0, 0)][DBLP]
    ASAP, 2006, pp:15-18 [Conf]
  5. Yong Ki Lee, Herwin Chan, Ingrid Verbauwhede
    Throughput Optimized SHA-1 Architecture Using Unfolding Transformation. [Citation Graph (0, 0)][DBLP]
    ASAP, 2006, pp:354-359 [Conf]
  6. David Hwang, Bo-Cheng Lai, Patrick Schaumont, Ingrid Verbauwhede
    A Security Protocol for Biometric Smart Cards. [Citation Graph (0, 0)][DBLP]
    CARDIS, 2002, pp:- [Conf]
  7. Kris Tiri, Ingrid Verbauwhede
    Place and Route for Secure Standard Cell Design. [Citation Graph (0, 0)][DBLP]
    CARDIS, 2004, pp:143-158 [Conf]
  8. Yusuke Matsuoka, Patrick Schaumont, Kris Tiri, Ingrid Verbauwhede
    Java cryptography on KVM and its performance and security optimization using HW/SW co-design techniques. [Citation Graph (0, 0)][DBLP]
    CASES, 2004, pp:303-311 [Conf]
  9. Ingrid Verbauwhede, Patrick Schaumont
    The happy marriage of architecture and application in next-generation reconfigurable systems. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2004, pp:363-376 [Conf]
  10. Lejla Batina, David Hwang, Alireza Hodjat, Bart Preneel, Ingrid Verbauwhede
    Hardware/Software Co-design for Hyperelliptic Curve Cryptography (HECC) on the 8051µP. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:106-118 [Conf]
  11. Henry Kuo, Ingrid Verbauwhede
    Architectural Optimization for a 1.82Gbits/sec VLSI Implementation of the AES Rijndael Algorithm. [Citation Graph (0, 0)][DBLP]
    CHES, 2001, pp:51-64 [Conf]
  12. Kris Tiri, David Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede
    Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:354-365 [Conf]
  13. Kris Tiri, Ingrid Verbauwhede
    Securing Encryption Algorithms against DPA at the Logic Level: Next Generation Smart Card Technology. [Citation Graph (0, 0)][DBLP]
    CHES, 2003, pp:125-136 [Conf]
  14. Kazuo Sakiyama, Lejla Batina, Bart Preneel, Ingrid Verbauwhede
    Superscalar Coprocessor for High-Speed Curve-Based Cryptography. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:415-429 [Conf]
  15. Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede
    Microcoded coprocessor for embedded secure biometric authentication systems. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:130-135 [Conf]
  16. Nele Mentens, Lejla Batina, Bart Preneel, Ingrid Verbauwhede
    A Systematic Evaluation of Compact Hardware Implementations for the Rijndael S-Box. [Citation Graph (0, 0)][DBLP]
    CT-RSA, 2005, pp:323-333 [Conf]
  17. Mustafa Badaroglu, Kris Tiri, Stéphane Donnay, Piet Wambacq, Hugo De Man, Ingrid Verbauwhede, Georges G. E. Gielen
    Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:399-404 [Conf]
  18. Rajesh K. Gupta, Shishpal Rawat, Ingrid Verbauwhede, Gérard Berry, Ramesh Chandra, Daniel Gajski, Kris Konigsfeld, Patrick Schaumont
    Panel: The Next HDL: If C++ is the Answer, What was the Question? [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:71-72 [Conf]
  19. David Hwang, Bo-Cheng Lai, Patrick Schaumont, Kazuo Sakiyama, Yi Fan, Shenglin Yang, Alireza Hodjat, Ingrid Verbauwhede
    Design flow for HW / SW acceleration transparency in the thumbpod secure embedded system. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:60-65 [Conf]
  20. Patrick Schaumont, Henry Kuo, Ingrid Verbauwhede
    Unlocking the design secrets of a 2.29 Gb/s Rijndael processor. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:634-639 [Conf]
  21. Patrick Schaumont, Bo-Cheng Charles Lai, Wei Qin, Ingrid Verbauwhede
    Cooperative multithreading on 3mbedded multiprocessor architectures enables energy-scalable design. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:27-30 [Conf]
  22. Patrick Schaumont, Ingrid Verbauwhede, Kurt Keutzer, Majid Sarrafzadeh
    A Quick Safari Through the Reconfiguration Jungle. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:172-177 [Conf]
  23. Kris Tiri, David Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede
    A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:222-227 [Conf]
  24. Kris Tiri, Ingrid Verbauwhede
    Simulation models for side-channel information leaks. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:228-233 [Conf]
  25. Ingrid Verbauwhede, Chris J. Scheers, Jan M. Rabaey
    Memory Estimation for High Level Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:143-148 [Conf]
  26. Patrick Schaumont, Sandeep K. Shukla, Ingrid Verbauwhede
    Design with race-free hardware semantics. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:571-576 [Conf]
  27. Patrick Schaumont, Ingrid Verbauwhede
    Interactive Cosimulation with Partial Evaluation. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:642-647 [Conf]
  28. Kris Tiri, Ingrid Verbauwhede
    A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:246-251 [Conf]
  29. Kris Tiri, Ingrid Verbauwhede
    Design Method for Constant Power Consumption of Differential Logic Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:628-633 [Conf]
  30. Kris Tiri, Ingrid Verbauwhede
    A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:58-63 [Conf]
  31. Ingrid Verbauwhede, Patrick Schaumont, Christian Piguet, Bart Kienhuis
    Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:988-995 [Conf]
  32. Oreste Villa, Patrick Schaumont, Ingrid Verbauwhede, Matteo Monchiero, Gianluca Palermo
    Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:804-805 [Conf]
  33. Herwin Chan, Patrick Schaumont, Ingrid Verbauwhede
    Process Isolation for Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:164-170 [Conf]
  34. Lejla Batina, Nele Mentens, Kazuo Sakiyama, Bart Preneel, Ingrid Verbauwhede
    Low-Cost Elliptic Curve Cryptography for Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP]
    ESAS, 2006, pp:6-17 [Conf]
  35. Ingrid Verbauwhede, Frank Hoornaert, Joos Vandewalle, Hugo De Man
    Security Considerations in the Design and Implementation of a new DES chip. [Citation Graph (0, 0)][DBLP]
    EUROCRYPT, 1987, pp:287-300 [Conf]
  36. Alireza Hodjat, Ingrid Verbauwhede
    A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:308-309 [Conf]
  37. Kris Tiri, Ingrid Verbauwhede
    Secure Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1052-1056 [Conf]
  38. Alireza Hodjat, David Hwang, Bo-Cheng Lai, Kris Tiri, Ingrid Verbauwhede
    A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-µm CMOS technology. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:60-63 [Conf]
  39. Kazuo Sakiyama, Elke De Mulder, Bart Preneel, Ingrid Verbauwhede
    Side-channel resistant system-level design flow for public-key cryptography. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:144-147 [Conf]
  40. Nele Mentens, Kazuo Sakiyama, Bart Preneel, Ingrid Verbauwhede
    Efficient pipelining for modular multiplication architectures in prime fields. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:534-539 [Conf]
  41. Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, Ingrid Verbauwhede
    Energy and Performance Analysis of Mapping Parallel Multithreaded Tasks for An On-Chip Multi-Processor System. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:102-104 [Conf]
  42. Lejla Batina, Nele Mentens, Ingrid Verbauwhede
    Side-Channel Issues for Designing Secure Hardware Implementations. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:118-121 [Conf]
  43. Doris Ching, Patrick Schaumont, Ingrid Verbauwhede
    Integrated Modeling and Generation of a Reconfigurable Network-on-Chip. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  44. Patrick Schaumont, Kazuo Sakiyama, Alireza Hodjat, Ingrid Verbauwhede
    Embedded Software Integration for Coarse-Grain Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  45. Bo-Cheng Lai, David Hwang, Sungha Pete Kim, Ingrid Verbauwhede
    Reducing radio energy consumption of key management protocols for wireless sensor networks. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:351-356 [Conf]
  46. Ingrid Verbauwhede, Chris Nicol
    Low power DSP's for wireless communications (embedded tutorial session). [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:303-310 [Conf]
  47. Alireza Hodjat, Ingrid Verbauwhede
    Minimum Area Cost for a 30 to 70 Gbits/s AES Processor. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:83-88 [Conf]
  48. Herwin Chan, Alireza Hodjat, Jun Shi, Richard D. Wesel, Ingrid Verbauwhede
    Streaming Encryption for a Secure Wavelength and Time Domain Hopped Optical Network. [Citation Graph (0, 0)][DBLP]
    ITCC (2), 2004, pp:578-582 [Conf]
  49. Alireza Hodjat, David Hwang, Ingrid Verbauwhede
    A Scalable and High Performance Elliptic Curve Processor with Resistance to Timing Attacks. [Citation Graph (0, 0)][DBLP]
    ITCC (1), 2005, pp:538-543 [Conf]
  50. Alireza Hodjat, Patrick Schaumont, Ingrid Verbauwhede
    Architectural Design Features of a Programmable High Throughput AES Coprocessor. [Citation Graph (0, 0)][DBLP]
    ITCC (2), 2004, pp:498-502 [Conf]
  51. Kris Tiri, Patrick Schaumont, Ingrid Verbauwhede
    Side-Channel Leakage Tolerant Architectures. [Citation Graph (0, 0)][DBLP]
    ITNG, 2006, pp:204-209 [Conf]
  52. Patrick Schaumont, Sandeep K. Shukla, Ingrid Verbauwhede
    Extended abstract: a race-free hardware modeling language. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2005, pp:255-256 [Conf]
  53. Kazuo Sakiyama, Patrick Schaumont, David Hwang, Ingrid Verbauwhede
    Teaching Trade-offs in System-level Design Methodologies. [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:62-53 [Conf]
  54. Ingrid Verbauwhede, M.-C. Frank Chang
    Reconfigurable interconnect for next generation systems. [Citation Graph (0, 0)][DBLP]
    SLIP, 2002, pp:71-74 [Conf]
  55. Patrick Schaumont, Ingrid Verbauwhede
    Domain-Specific Codesign for Embedded Security. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2003, v:36, n:4, pp:68-74 [Journal]
  56. Patrick Schaumont, Ingrid Verbauwhede
    A Component-Based Design Environment for ESL Design. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:5, pp:338-347 [Journal]
  57. David Hwang, Patrick Schaumont, Kris Tiri, Ingrid Verbauwhede
    Securing Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Security & Privacy, 2006, v:4, n:2, pp:40-49 [Journal]
  58. Alireza Hodjat, Lejla Batina, David Hwang, Ingrid Verbauwhede
    HW/SW co-design of a hyperelliptic curve cryptosystem using a microcode instruction set coprocessor. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:1, pp:45-51 [Journal]
  59. Alireza Hodjat, Ingrid Verbauwhede
    High-Throughput Programmable Cryptocoprocessor. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:3, pp:34-45 [Journal]
  60. Alireza Hodjat, Ingrid Verbauwhede
    Area-Throughput Trade-Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:4, pp:366-372 [Journal]
  61. Patrick Schaumont, David Hwang, Shenglin Yang, Ingrid Verbauwhede
    Multilevel Design Validation in a Secure Embedded System. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:11, pp:1380-1390 [Journal]
  62. Mustafa Badaroglu, Kris Tiri, Geert Van der Plas, Piet Wambacq, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
    Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1146-1154 [Journal]
  63. Patrick Schaumont, David Hwang, Ingrid Verbauwhede
    Platform-based design for an embedded-fingerprint-authentication device. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:12, pp:1929-1936 [Journal]
  64. Kris Tiri, Ingrid Verbauwhede
    A digital design flow for secure integrated circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1197-1208 [Journal]
  65. Ingrid Verbauwhede, Patrick Schaumont
    Skiing the embedded systems mountain. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2005, v:4, n:3, pp:529-548 [Journal]
  66. Patrick Schaumont, Doris Ching, Ingrid Verbauwhede
    An interactive codesign environment for domain-specific coprocessors. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:70-87 [Journal]
  67. Ingrid Verbauwhede, Patrick Schaumont
    Design methods for security and trust. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:672-677 [Conf]
  68. Nele Mentens, Kazuo Sakiyama, Lejla Batina, Ingrid Verbauwhede, Bart Preneel
    Fpga-Oriented Secure Data Path Design: Implementation of a Public Key Coprocessor. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  69. Dries Schellekens, Bart Preneel, Ingrid Verbauwhede
    FPGA Vendor Agnostic True Random Number Generator. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  70. Lejla Batina, Alireza Hodjat, David Hwang, Kazuo Sakiyama, Ingrid Verbauwhede
    Reconfigurable Architectures for Curve-Based Cryptography on Embedded Micro-Controllers. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-4 [Conf]
  71. Lejla Batina, Nele Mentens, Kazuo Sakiyama, Bart Preneel, Ingrid Verbauwhede
    Public-Key Cryptography on the Top of a Needle. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1831-1834 [Conf]
  72. Kazuo Sakiyama, Bart Preneel, Ingrid Verbauwhede
    A fast dual-field modular arithmetic logic unit and its hardware implementation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  73. Lejla Batina, Nele Mentens, Bart Preneel, Ingrid Verbauwhede
    Flexible hardware architectures for curve-based cryptography. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  74. Nele Mentens, Kazuo Sakiyama, Lejla Batina, Bart Preneel, Ingrid Verbauwhede
    A Side-channel Attack Resistant Programmable PKC Coprocessor for Embedded Applications. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:194-200 [Conf]
  75. Kazuo Sakiyama, Nele Mentens, Lejla Batina, Bart Preneel, Ingrid Verbauwhede
    Reconfigurable Modular Arithmetic Logic Unit for High-Performance Public-Key Cryptosystems. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:347-357 [Conf]
  76. Nele Mentens, Lejla Batina, Bart Preneel, Ingrid Verbauwhede
    Time-Memory Trade-Off Attack on FPGA Platforms: UNIX Password Cracking. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:323-334 [Conf]
  77. Oreste Villa, Patrick Schaumont, Ingrid Verbauwhede, Matteo Monchiero, Gianluca Palermo
    Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  78. Kris Tiri, Ingrid Verbauwhede
    Design Method for Constant Power Consumption of Differential Logic Circuits [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  79. Kris Tiri, Ingrid Verbauwhede
    A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  80. Kazuo Sakiyama, Lejla Batina, Bart Preneel, Ingrid Verbauwhede
    Multicore Curve-Based Cryptoprocessor with Reconfigurable Modular Arithmetic Logic Units over GF(2n). [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:9, pp:1269-1282 [Journal]
  81. Jongsun Kim, Ingrid Verbauwhede, M.-C. Frank Chang
    Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:881-894 [Journal]
  82. E. Macii, Ingrid Verbauwhede
    Guest editorial: low-power electronics and design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:2, pp:69-70 [Journal]
  83. Elke De Mulder, Siddika Berna Örs, Bart Preneel, Ingrid Verbauwhede
    Differential power and electromagnetic attacks on a FPGA implementation of elliptic curve cryptosystems. [Citation Graph (0, 0)][DBLP]
    Computers & Electrical Engineering, 2007, v:33, n:5-6, pp:367-382 [Journal]
  84. Kazuo Sakiyama, Lejla Batina, Bart Preneel, Ingrid Verbauwhede
    HW/SW co-design for public-key cryptosystems on the 8051 micro-controller. [Citation Graph (0, 0)][DBLP]
    Computers & Electrical Engineering, 2007, v:33, n:5-6, pp:324-332 [Journal]

  85. Low-cost implementations of NTRU for pervasive security. [Citation Graph (, )][DBLP]


  86. On the high-throughput implementation of RIPEMD-160 hash algorithm. [Citation Graph (, )][DBLP]


  87. Hardware evaluation of the Luffa hash family. [Citation Graph (, )][DBLP]


  88. Power and Fault Analysis Resistance in Hardware through Dynamic Reconfiguration. [Citation Graph (, )][DBLP]


  89. Programmable and Parallel ECC Coprocessor Architecture: Tradeoffs between Area, Speed and Security. [Citation Graph (, )][DBLP]


  90. Low-Overhead Implementation of a Soft Decision Helper Data Algorithm for SRAM PUFs. [Citation Graph (, )][DBLP]


  91. Faster -Arithmetic for Cryptographic Pairings on Barreto-Naehrig Curves. [Citation Graph (, )][DBLP]


  92. Fault Analysis Study of IDEA. [Citation Graph (, )][DBLP]


  93. Revisiting Higher-Order DPA Attacks: . [Citation Graph (, )][DBLP]


  94. FPGA Design for Algebraic Tori-Based Public-Key Cryptography. [Citation Graph (, )][DBLP]


  95. An embedded platform for privacy-friendly road charging applications. [Citation Graph (, )][DBLP]


  96. Case Study : A class E power amplifier for ISO-14443A. [Citation Graph (, )][DBLP]


  97. Exploiting Hardware Performance Counters. [Citation Graph (, )][DBLP]


  98. Random numbers generation: Investigation of narrowtransitions suppression on FPGA. [Citation Graph (, )][DBLP]


  99. Partition vs. Comparison Side-Channel Distinguishers: An Empirical Evaluation of Statistical Tests for Univariate Side-Channel Attacks against Two Unprotected CMOS Devices. [Citation Graph (, )][DBLP]


  100. FPGA-based testing strategy for cryptographic chips: A case study on Elliptic Curve Processor for RFID tags. [Citation Graph (, )][DBLP]


  101. Public-Key Cryptography for RFID-Tags. [Citation Graph (, )][DBLP]


  102. Perfect Matching Disclosure Attacks. [Citation Graph (, )][DBLP]


  103. HECC Goes Embedded: An Area-Efficient Implementation of HECC. [Citation Graph (, )][DBLP]


  104. Practical Mitigations for Timing-Based Side-Channel Attacks on Modern x86 Processors. [Citation Graph (, )][DBLP]


  105. Iteration Bound Analysis and Throughput Optimum Architecture of SHA-256 (384, 512) for Hardware Implementations. [Citation Graph (, )][DBLP]


  106. A Compact Architecture for Montgomery Elliptic Curve Scalar Multiplication Processor. [Citation Graph (, )][DBLP]


  107. Revisiting a combinatorial approach toward measuring anonymity. [Citation Graph (, )][DBLP]


  108. Modular Reduction in GF(2n) without Pre-computational Phase. [Citation Graph (, )][DBLP]


  109. Speeding Up Bipartite Modular Multiplication. [Citation Graph (, )][DBLP]


  110. Low-cost untraceable authentication protocols for RFID. [Citation Graph (, )][DBLP]


  111. Unified Digit-Serial Multiplier and Inverter in Finite Field GF(2m). [Citation Graph (, )][DBLP]


  112. Analysis and Design of Active IC Metering Schemes. [Citation Graph (, )][DBLP]


  113. Montgomery Modular Multiplication Algorithm on Multi-Core Systems. [Citation Graph (, )][DBLP]


  114. A digit-serial architecture for inversion and multiplication in GF(2M). [Citation Graph (, )][DBLP]


  115. On the Practical Performance of Rateless Codes. [Citation Graph (, )][DBLP]


Search in 0.015secs, Finished in 0.024secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002