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Arnaldo Azevedo: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Rodrigo Soares, Arnaldo Azevedo, Ivan Saraiva Silva
    X4CP32: A Coarse Grain General Purpose Reconfigurable Microprocessor. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:171- [Conf]
  2. Bruno Zatt, Arnaldo Azevedo, Luciano Volcan Agostini, Altamiro Amadeu Susin, Sergio Bampi
    Memory Hierarchy Targeting Bi-Predictive Motion Compensation for H.264/AVC Decoder. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:445-446 [Conf]
  3. Arnaldo Azevedo, Luciano Volcan Agostini, Flávio Rech Wagner, Sergio Bampi
    Accelerating a Multiprocessor Reconfigurable Architecture with Pipelined VLIW Units. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:255-257 [Conf]
  4. Rodrigo Soares, Arnaldo Azevedo, Ivan Saraiva Silva
    X4CP32: A New Parallel/Reconfigurable General-Purpose Processor. [Citation Graph (0, 0)][DBLP]
    SBAC-PAD, 2003, pp:260-268 [Conf]
  5. Rodrigo Soares, Ivan Saraiva Silva, Arnaldo Azevedo
    When reconfigurable architecture meets network-on-chip. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:216-221 [Conf]
  6. Arnaldo Azevedo, Rodrigo Soares, Ivan Saraiva Silva
    A New Hybrid Parallel/Reconfigurable Architecture: The X4CP32. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:225-230 [Conf]
  7. Luciano Volcan Agostini, Arnaldo Azevedo, Vagner S. Rosa, Eduardo A. Berriel, Tatiana G. S. dos Santos, Sergio Bampi, Altamiro Amadeu Susin
    FPGA Design of A H.264/AVC Main Profile Decoder for HDTV. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  8. Arnaldo Azevedo, Bruno Zatt, Luciano Volcan Agostini, Sergio Bampi
    MoCHA: a Bi-Predictive Motion Compensation Hardware for H.264/AVC Decoder Targeting HDTV. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1617-1620 [Conf]
  9. Vagner S. Rosa, Wagston T. Staehler, Arnaldo Azevedo, Bruno Zatt, Roger E. Porto, Luciano Volcan Agostini, Sergio Bampi, Altamiro Amadeu Susin
    FPGA Prototyping Strategy for a H.264/AVC Video Decoder. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2007, pp:174-180 [Conf]
  10. Arnaldo Azevedo, Bruno Zatt, Luciano Volcan Agostini, Sergio Bampi
    Motion Compensation Decoder Architecture for H.264/AVC Main Profile Targeting HDTV. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:52-57 [Conf]

  11. Analyzing Scalability of Deblocking Filter of H.264 via TLP Exploitation in a New Many-Core Architecture. [Citation Graph (, )][DBLP]


  12. Parallel H.264 Decoding on an Embedded Multicore Processor. [Citation Graph (, )][DBLP]


  13. Analysis of video filtering on the cell processor. [Citation Graph (, )][DBLP]


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