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Publications of Author

1. Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
   Hierarchical Clustered Register File Organization for VLIW Processors. [Citation Graph (0, 0)][DBLP]
   IPDPS, 2003, pp:77- [Conf]
   
2. Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero
   Power-Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes. [Citation Graph (0, 0)][DBLP]
   ISHPC, 2003, pp:113-126 [Conf]
   
3. Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
   MIRS: Modulo Scheduling with Integrated Register Spilling. [Citation Graph (0, 0)][DBLP]
   LCPC, 2001, pp:239-253 [Conf]
   
4. Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
   Two-level hierarchical register file organization for VLIW processors. [Citation Graph (0, 0)][DBLP]
   MICRO, 2000, pp:137-146 [Conf]
   
5. Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
   Modulo scheduling with integrated register spilling for clustered VLIW architectures. [Citation Graph (0, 0)][DBLP]
   MICRO, 2001, pp:160-169 [Conf]
   
6. Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
   Improved spill code generation for software pipelined loops. [Citation Graph (0, 0)][DBLP]
   PLDI, 2000, pp:134-144 [Conf]
   
7. Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero
   with Wide Functional Units. [Citation Graph (0, 0)][DBLP]
   SAMOS, 2004, pp:88-97 [Conf]
   
8. Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
   Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures. [Citation Graph (0, 0)][DBLP]
   International Journal of Parallel Programming, 2004, v:32, n:6, pp:447-474 [Journal]
   
9. Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
   Register Constrained Modulo Scheduling. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Parallel Distrib. Syst., 2004, v:15, n:5, pp:417-430 [Journal]