Search the dblp DataBase

Publications of Author

1. V. Rao, N. Navet, G. Singhal, A. Kumar, G. S. Visweswaran
   Battery aware dynamic scheduling for periodic task graphs. [Citation Graph (0, 0)][DBLP]
   IPDPS, 2006, pp:- [Conf]
   
2. Basabi Bhaumik, Pravas Pradhan, G. S. Visweswaran, Rajamohan Varambally, Anand Hardi
   A Low Power 256 KB SRAM Design. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1999, pp:67-71 [Conf]
   
3. Basabi Bhaumik, G. S. Visweswaran, R. Lakshminarasimhan
   A New Test Compression Scheme. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1999, pp:95-99 [Conf]
   
4. Sanjeev Kumar Maheshwari, R. S. Krishanan, G. S. Visweswaran
   Jitter Estimation Methodology for Clock Chips. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2000, pp:480-482 [Conf]
   
5. Sanjeev Kumar Maheshwari, G. S. Visweswaran
   A 3.3V Compatible 2.5V TTL-to-CMOS Bidirectional I/O Buffer. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2000, pp:484-487 [Conf]
   
6. Saeid Nooshabadi, Juan A. Montiel-Nelson, G. S. Visweswaran, D. Nagchoudhuri
   Micropipeline Architecture for Multiplier-less FIR Filters. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1997, pp:451-456 [Conf]
   
7. Saeid Nooshabadi, G. S. Visweswaran, D. Nagchoudhuri
   Current Mode Ternary D/A Converter. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1998, pp:244-248 [Conf]
   
8. Mukul Milind Ojha, Arun Kumar Anand, G. S. Visweswaran, D. Nagchoudhuri
   A Relative Comparative Based Datapath for Increasing Resolution in a Capacitive Fingerprint Sensor Chip. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2005, pp:828-831 [Conf]
   
9. Tushar S. Shelar, G. S. Visweswaran
   Inclusion of Thermal Effects in the Simulation of Bipolar Circuits using Circuit Level Behavioral Modeling. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2004, pp:821-826 [Conf]
   
10. 
    Texture filter memory: a power-efficient and scalable texture memory architecture for mobile graphics processors. [Citation Graph (, )][DBLP]
    
    
11. 
    Novel Digital Differentiator and Corresponding Fractional Order Differentiator Models. [Citation Graph (, )][DBLP]